Help: ICE_JVCC_LANGUAGE:

The JavaVerilog language follows Java 1.6 constructs with the following extensions:

The JavaVerilog language follows Java 1.6 constructs with the following extensions:

Integer data types can specify the number of bits, ex. int6 for a 6 bit integer.
The Verilog syntax for selecting bit ranges of an integer is also adopted.
For example:  myint[5:3] refers to bits 3 through 5 of the integer myint,
and myint[5] refers to bit 5 of the integer cast as a boolean.
To unpack bits of a vector, packed(a,b,c) performs the verilog {a,b,c} = XXX.
To pack bits into a vector, packL(a,b,c) performs the verilog XXX = {a,b,c}.
All right shifts ">>" are converted to arithmetic shifts ">>>" in verilog.

Fixed floating point types fptx and dptx are introduced to support FPGA platforms
that do not efficiently support IEEE floating point arithmetic.