Help: ICE_JVCC_FPGA_IMPLEMENTATION

Most of the methods in a Core are for setup and parsing and do not execute in FPGA hardware.

Most of the methods in a Core are for setup and parsing and do not execute in FPGA hardware.
All methods with names that begin with "process" are implemented in the FPGA.

The compiler assumes a synchronous design methodology in the FPGA. The system clock is used 
to supply all control interfaces as well as read the input stream/buffer and write the output 
stream/buffer.  Most statements will use this clock.  A 2x clock is available for special loops.  

The coreName.sv file contains three sections: Declarations, Sequencer, and Execution.

The variables in the declarations section are allocated much as they are in C. 
All other statements are then evaluated for input and output variable execution sensitivity.

The sequencer section uses the sensitivity list to decide which clock on which to execute each 
line of code.  Loops are unrolled in time by default.  When pipelined, many of these lines are 
executing simultaneously.  Each equals sign (or other form of assignment) infers a clock edge.
Complex equations can be split into simpler equations of similar complexity and combined 
on the next line to improve timing. 

The execution section implements the assignment statements in a single always block except for 
unrolled loops that are converted to unique generate-for loops with their own 1x or 2x clock.