Help: ICE_JVCC_COMPILER

The JVCC cross compiler takes in a Java/Verilog coreName.jv file and generates the

The JVCC cross compiler takes in a Java/Verilog coreName.jv file and generates the 
source code for each of the different platforms.  This includes coreName.java for 
a JVM, coreName.c for a CPU, and coreName.sv for an FPGA supporting SystemVerilog.

The Java and C versions are self contained and will run on any JVM or CPU.  

The SystemVerilog version contains instances of Java objects converted into
System Verilog modules that can be compiled into .bit files on Xilinx, Altera 
or any other FPGA supporting SystemVerilog.  In this case, the library calls in 
the C code initialize the objects, load the initial class variables into the FPGA, 
and start the data flow to execute the core's processing methods in the hardware 
device.