Help: ICE_JVCC

The ICE-CORE (Code-Once-Run-Everywhere) framework is intended to simplify 
algorithm development and deployment by using a single test and development
methodology when writing code that runs on different platforms such as 
CPUs, GPUs, VPUs and FPGAs.

The maintenance of these source files can be reduced in many situations by using
the ICE-JVCC cross compiler.  We define a new language, JavaVerilog, that has the 
information necessary to automatically generate the Java, C, and SystemVerilog 
code for various platforms.

  COMPILER - The JVCC cross compiler takes in a Java/Verilog coreName.jv file and generates the
  LANGUAGE - The JavaVerilog language follows Java 1.6 constructs with the following extensions:
  DATA_FLOWS - The current JVCC supports four processing flows: Stream, Buffer, Packet and Array.
  DATA_TYPES - The Java language supports primitive data types of byte, short, int, long, float and
  DATA_STRUCTURES - To define data structures that do not have class methods or constructors, the class
  CORES - Cores are objects that can be accessed by the external world
  COMPONENT - Components are blocks of code that implement functions that may be used by this core
  FUNCTIONS - Functions for commonly used C math functions are available as methods in the CoreCommon
  TASKS - Tasks are functions that may take multiple clock cycles in the FPGA version
  DECLARATIONS - Although Java and Verilog support declarations almost anywhere in the code, to keep the C
  DEFINES - All static declarations in the JV code are converted to defines in the C and FPGA code.
  FPGA_IMPLEMENTATION - Most of the methods in a Core are for setup and parsing and do not execute in FPGA hardware.
  DIRECTIVES - The compiler can be given directives to tune its behavior
  DEFINES - The source code is also parsed for the following special defines.