Help: ICE_FLAGS_FTTM=N

Fast Tuner Transform Mode controls various bank of tuners algorithms.

Fast Tuner Transform Mode controls various bank of tuners algorithms.

  FTTM<0 Auto detect FTTM mode
  FTTM=0 Shared dma channel, same decimation, FFT based channelizer (1024 chan/side)
  FTTM=1 Shared dma channel, same decimation, set freq spacing, single pass (16 chan/side)
  FTTM=2 Shared dma channel, same decimation, set freq spacing, two passes, A/B locked, (128 chan/side)
  FTTM=3 Shared dma channel, same decimation, set freq spacing, three passes, A/B locked, (2048 chan/side)

By default, the tuners have FTTM turned off.  With FTTM=0 an FFT based approach is used
requiring a special PMFPGA=bt flag to load the FPGA.  With FTTM>1 on a processor module, 
the FTT algorithm allows the tuner chips/cores to produce more channels than the FTTM=1 
straight through approach.  The algorithm uses half of the chips/cores to select blocks 
of the spectrum from the wideband input and write them to memory.  The other chips/cores 
are used to further process these streams into individual channels.  

FTTM==1

The tuners are run single pass with independent frequency, gain, and filters.  The outputs are
collected in memory until a packet length of data is available for each channel.  The data for 
one packet for each channel are streamed in sequence through a single DMA channel.  The host
code then seperates each packet to an individual channel stream or a single stream with packet
headers denoting the channel number for each packet.

FTTM>1

The algorithm with FTTM>1 will attempt to determine the following operational parameters on its own, 
but you can override these by specifying the following flags:

  FTTD1=n Initial up front decimation
  FTTN1=n Initial up front channels
  FTTD2=n Stage 2 decimation
  FTTN2=n Stage 2 channels
  FTTD3=n Stage 3 decimation
  FTTN3=n Stage 3 channels

The resampler can only be used if the ratio can be expressed as (P/X)*D2 where both P and
X are a multiple of 64 bytes.  X is the transfer length into the stage 2 tuners <= 512K.
P is the stage 2 tuner production length <= 64K.  The graychips do not support setting the
resampler phase, so it must start and end each pass at phase=0.  

  FTTX2=n Stage 2 transfer length
  FTTP2=n Stage 2 produce length

The front end tuner gains are set by the standard gain parameter.  To set the gain in the
2nd and 3rd stage, use:

  FTTG2=n Stage 2+ gain 

The number of usable channels depends on the FTTM mode, decimation, and channel spacing.
The CHNS=n flag can be used to limit the number of channels output to less than the
default of N1*N2*N3.

There are a number of restrictions.  Apply the VERBOSE flag to see the actual parameters used.
Resampling is applied to the last stage only.

FTTM==0

With FTTM=0, an FFT approach is used to affect a similar output.  The complex input data is 
run through two polyphase FFTs with a cell width of twice the channel spacing and offset by
one channel.  The output of each cell in time is then processed through a resampler filter
with a nominal bandwidth of 1/2 of the cell frequency (the channel spacing). The resample ratio
must be between 1 and 4. The input sample rate must be chosen such that Fs is equal to the 
channel spacing times the FFT size which must be a power of 2 between 64 and 2048.