Help: ICE_CORES_ADDRESSING

Register addressing rules

Each core has a set of 32bit wide registers that are read/writable through the
pic_setkey, pic_getkey, pic_wpm, and pic_rpm routines.  Each core has a 24 bit 
register address window with a base address (upper 8 bits) defined in iceppc.h.
Use the FLG_PPC_BUS flag on pic_wpm and pic_rpm calls to address the system 
register bus and the KEY_CORE key for the pic_setkey and pic_getkey calls.

The first register address is the System register set by the system software whenever a core is activated.

  0) System Register (bit 0 is enable, bit 1 is play/acq, bits[11:8] input format, [15:12] output format))

  Input/Output formats: bit[2:0]? 0=16b 1=8b 2=4b 3=1b 4=32b  bit[3]?complex:real

The next 7 register addresses are pre-defined and set by every call to pic_ioport on a CORE or MCORE.

  1) DEC   - Decimation (dec-1)
  2) GAIN  - Gain
  3) RATE  - Rate (Hz)
  4) RATIO - Ratio (fractional binary)
  5) FRAME - Frame (frame-1)
  6) FREQ  - Frequency (fractional binary)
  7) FLAG  - Flags

The next 8 are reserved for other system routines.

  8..15) Filter coef loaders

The rest are available for user core parameters.

 16..255) User parameters for each multicore.
 16..1M)  User parameters for each core.

The user registers are not written or cleared by system software.

See the help on each of these routines for detailed syntax.