Help: ICE_CORES

This file contains a brief description of the current interface for user
FPGA cores within the ICE FPGA architecture.  An ICE Core is an FPGA module
with a set of function registers, two dataflow ports, and a test output port.  

The verilog implementation signature looks like this:

  module #(PORT,IBW,OBW) userengine 
	(sclk,srst, scs,saddr, swr,swrbus, srd,srdbus, sack,
	ioclk, istat,iena,isel,ibus, ostat,oena,osel,obus, test);
or

  module #(PORT,IBW,OBW) mcengine 
	(sclk,srst, scs,saddr, swr,swrbus, srd,srdbus, sack,
	ioclk, istat,iena,isel,ibus, ostat,oena,osel,obus, test);

The MultiCore engines are used to handle channelized functions.  
They can contain 1-16 single channel cores using a common input stream.
or 1-16 single channel cores combined into a common output stream.
Noramlly, the mcengine.v in the ICE tree is used to call N userengines.

If you have access to the ICE FPGA development tree, the example files are
$ICEROOT/code/soc/user/userengine.v and $ICEROOT/code/soc/user/User.jv .

The userengine.v code is an example of a basic core. The control interface 
consists of eight 32 bit standard registers and eight user defined registers
that can be manipulated with standard configuration flags. For example:

  flags = "ICEPIC,...,CORE=(DEC=3,USER1=0x80,USER2=123)
or
  ICECORE/core=I ifile ofile "HOC" DEC=3 USER1=0x80 USER2=123 
or
  ICECORE/core=I ifile ofile "HOC" /cfg={DEC=3,USER1=0x80,USER2=123}

where "HOC" is a generic control wrapper for a Hardware-Only-Core. These cores
can call any other verilog callable modules including VHDL, NGC, or DCP cores.

The User.jv code is an example of a JVCC core.  The control interfase consists
of auto-generated C code that is called using the ICECORE primitive or dynamically 
linked into the ICE library at runtime with flags. For example:

  flags = "ICEPIC,...,CORE=(NAME=AWG,MOD=QPSK,BAUD=1e6,FEC=TCM23)
or
  ICECORE/core=I ifile ofile "AWG" MOD=QPSK BAUD=1e6 FEC=TCM23

In the Midas environment, the ICECORE primitive generates run-time controls 
for each of its parameters where the flags implementation does not.

  INSTALLATION - Installing the ICE tree for Core development
  SPICE - Signal Processing Integrated Coding Environment development GUI
  SETUP - Setting up a basic core for use in a dataflow
  NAMING - Core naming rules
  ADDRESSING - Register addressing rules
  ROUTING - data routing rules
  DMA - DMA Crossbar functionality
  TRACER - Embedded FPGA debug trace mechanism