ICEJVCC

Java Verilog Cross Compiler for ICE Cores.

ICEJVCC - Java Verilog Cross Compiler for ICE Cores

<in>     Input file 

Given a java-verilog source file, this command produces implmentations for execution
in a JVM, CPU, and FPGA.  The output files use the extensions, .java, .c, and .sv .

The syntax follows java 1.6 constructs with the following extensions:

Integer data types can specify the number of bits, ex. uint6 for a 6 bit integer.
Floating point types are fptx and dptx for 16.16 and 32.32 fractional fixed point on 
the FPGA.  In JDK and C implementations, these are handled by the native primitive types.

The Verilog syntax for selecting bit ranges of an integer is adopted for ease of use.
For example:  myint[5:3] refers to bits 3 through 5 of the integer myint.

The special routine packed() can be used to pack/unpack a struct into/from local variables.

All public class variables are copied to the class RAM block on the engine before execution.
Open is run first, then the process method multiple times in either a STREAM or BUFFER 
dataflow mode, followed by a close call.

For FPGA implementations, only the process methods are implemented on the engine.

Switches:
  /DEBUG	- include verbose activity printout