#!/bin/csh -f
#
# This is used to clean/compile/check/edit the ICE designs since the ISE is so pathetic
#
if ( $1 == "" ) then
  echo " "
  echo " xi <action> <design> <sig> <seed> <name>"
  echo " xi   make    v6m      ssu    1     UserX      -  hardware modules"
  echo " xi   make    sim      ss    opt    UserX      -  simulator modules"
  echo " "
  echo " actions = make|synth|par|config|edit|timing|plan|clean|clear|coregen|check|checkall"
  echo " design  = sim|dtdm|v6m|pic5|pic6|pic7 / sim for verilog simulator"
  echo " sig     = signature - see help on SOC / ss for sim"
  echo " seed    = seed [1-10] for fitter def=1 / option tree name for sim"
  echo " name    = override auto determination of processor engine PE from sig / core file name for sim"
  echo " "
  exit
endif

if ( $1 == "clear" ) then
  rm -rf ~/.wind* ~/.Wind*
  exit
endif

if (  $1 == "doc" || $1 == "docs" ) then
  if ($2 == 9 ) then
    kpdf $XILINX9/doc/usenglish/books/manuals.pdf &
  else if ($2 == 10 ) then
    kpdf $XILINX10/ISE/doc/usenglish/books/manuals.pdf &
  else if ($2 == 11 ) then
    kpdf $XILINX11/ISE/doc/usenglish/isehelp/manuals.pdf &
  else if ($2 == 12 ) then
    kpdf $XILINX12/ISE/doc/usenglish/isehelp/manuals.pdf &
  else if ($2 == 13 ) then
    konqueror $XILINX13/ISE/doc/usenglish/isehelp/manuals.pdf &
  else
    konqueror $XILINX14/ISE/doc/usenglish/isehelp/manuals.pdf &
  endif
  exit
endif

set action = $1
set design = $2
set sig    = $3
set seed   = $4
set name   = $5
set area   = $design
set root   = $0:h

# parse seed override out of sig:seed syntax
set iseed = `echo $sig | awk -F : '{ print $2 }' `
if ( _$iseed != _) then
  set sig = `echo $sig | awk -F : '{ print $1 }' `
  set seed = $iseed
endif

if ( _$sig == _ ) set sig = ssn
if ( _$seed == _ ) set seed = 1
set SIG = `echo $sig | sed -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/' `
set card = `echo $design | sed -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/' `

if ( $?ICE_FPGA_USER_DIR ) then
  setenv IFUD $ICE_FPGA_USER_DIR
else if ( $?IFUD ) then
  # use it
else if ( $design == "sim" ) then
  if ( $seed == "icex" ) then
    # verilog cores in IFUD, cores in nxm/ice/cores
    set seed = "ice"
    setenv IFUD $NMROOT/nxm/ice/code/soc/cores
  else
    # verilog and cores in nxm/$area/core
    setenv IFUD $NMROOT/nxm/$seed/core
  endif
else if ( _$name != _ ) then
  setenv IFUD $NMROOT/nxm/ice/core
endif

# parse USER number out of sig
set iuser = `echo $SIG | awk -F U '{ print $2 }' `

# card type
set vt = 2
set vs = "v"
set lanes = 0
set ped = DEF
set obf = OFF
if ( $design == sim ) then
  set part = none
  if ( _$name == _ ) then
    set name = $sig
    set sig = "ss"
  endif
endif
if ( $design == pic5 ) then
  set part = xc2vp40-5-ff1148
endif
if ( $design == pic6 || $design == pod6 ) then
  set part = xc4vfx60-10-ff1152
  set lanes = 8
  set vt = 4
endif
if ( $design == pod6 ) then
  set area = pic6
endif
if ( $design == pic7 ) then
  set part = xc7k325t-2-ffg900
  set lanes = 8
  set vt = 7
endif
if ( $design == pic8 ) then
  set part = xcku040-fbva900-2-i
  set lanes = 8
  set vt = 8
endif
if ( $design == pic8q ) then
  set area = pic8
  set part = xcku040-fbva900-2-i
  set lanes = 8
  set vt = 8
endif
if ( $design == pic8p ) then
  set part = xcvu35p-fsvh2104-2-e
#  set part = xcu50-fsvh2104-2L-e
  set lanes = 16
  set vt = 8
endif
if ( $design == pic9 ) then
  set part = AGFB027R24C2E2VR2
  set vt = 5
  set vs = "a"
endif
if ( $design == pac8 ) then
  set area = pic8
  set part = xcku040-fbva900-2-i
  set lanes = 8
  set vt = 8
endif
if ( $design == npac8 ) then
  set area = pic8
  set part = xcku040-fbva900-2-i
  set lanes = 8
  set vt = 8
endif
if ( $design == qpac8 ) then
  set area = pic8
  set part = xcku040-fbva900-2-i
  set lanes = 8
  set vt = 8
endif
if ( $design == spac8 ) then
  set area = pic8
  set part = xcku040-fbva900-2-i
  set lanes = 8
  set vt = 8
endif
if ( $design == cpac8 ) then
  set area = pic8
  set part = xcku040-fbva900-2-i
  set lanes = 8
  set vt = 8
endif
if ( $design == rfpac8 ) then
#  set part = xczu48dr-fsvg1517-2-e
  set part = xczu47dr-fsve1156-2-i
  set lanes = 8
  set vt = 8
endif
if ( $design == zcu208 ) then
  set part = xczu48dr-fsvg1517-2-e
  set lanes = 8
  set vt = 8
endif
if ( $design == upac8 ) then
  set area = pic8
  set part = xcku040-fbva900-2-i
  set lanes = 8
  set vt = 8
endif
if ( $design == pod8 ) then
  set area = pic8
  set part = xcku040-fbva900-2-i
  set lanes = 8
  set vt = 8
endif
if ( $design == pic8p_bw ) then
  set part = xcvu3p-ffvc1517-2-e
  set lanes = 16
  set vt = 8
endif
if ( $design == pic8p_vcu1525 ) then
  set part = xcvu9p-flga2104-2-e
  set part = xcvu9p-flga2104-2L-e
  set part = xcvu9p-fsgd2104-2L-e
  set lanes = 16
  set vt = 8
endif
if ( $design == k8m ) then
  set part = xcku040-fbva900-2-i
  set lanes = 8
  set vt = 8
  set obf = AUTO
endif
if ( $design == k8p ) then
  set part = xcku13p-ffve900-1-e
  set lanes = 8
  set vt = 8
  set area = k8m
  set obf = AUTO
endif
if ( $design == a8m ) then
  set part = 10AX066H2F34I2SGES
  set lanes = 8
  set vt = 8
endif
if ( $design == v6m ) then
  set part = xc6vlx240t-1-ff1156
  set vt = 6
endif
if ( $design == zppm ) then
  set part = xc5vsx95t-1-ff1136
  set vt = 5
endif
if ( $design == v5m ) then
  set part = xc5vlx110t-1-ff1738
  set vt = 5
endif
if ( $design == dtdm ) then
  set part = xc2vp7-5-ff672
  set ped = DMOD
endif
if ( $design == dtdmx ) then
  set part = xc2vp40-5-fg676
  set ped = DMOD
  set area = dtdm
endif
if ( $design == rfxd ) then
  set part = xc3s500e-5-ft256
  set vt = 3
  set vs = "s"
endif
if ( $design == a2dm14 ) then
  set part = xc6slx45-2-csg324
  set vt = 6
  set vs = "s"
endif
if ( $design == sp6 ) then
  set part = xc6slx150-3-fgg484
  set vt = 6
  set vs = "s"
endif
if ( $design == a2dm20x ) then
  set part = 10AX016E4F27E3SG
  set vt = 5
  set vs = "a"
  set area = a2dm20
endif
if ( $design == a2dm1x ) then
  set part = xc6slx150-3-fgg484
  set vt = 6
  set vs = "s"
endif
if ( $design == d2rf ) then
  set part = xc6slx150-3-fgg484
  set vt = 6
  set vs = "s"
endif
if ( $design == lb2dm3 ) then
  set part = xc6slx150-3-fgg484
  set vt = 6
  set vs = "s"
endif
if ( $design == lb2dm3x ) then
  set part = xc6slx150-3-fgg484
  set vt = 6
  set vs = "s"
  set area = lb2dm3
endif
if ( $design == d2awgm3 ) then
  set part = xc6slx150-3-fgg484
  set vt = 6
  set vs = "s"
endif
if ( $design == d2awgm3x ) then
  set part = xc6slx150-3-fgg484
  set vt = 6
  set vs = "s"
  set area = d2awgm3
endif
if ( $design == d2awgm3y ) then
  set part = xc6slx150-3-fgg484
  set vt = 6
  set vs = "s"
  set area = d2awgm3
endif
if ( $design == d2awgm3a ) then
  set part = xcau10p-sbvb484-1-e
  set vt = 8
  set vs = "r"
  set obf = AUTO
  set area = d2awgm3
endif
if ( $design == s6m ) then
  #set part = xc6slx75-2-fgg484
  set part = xc6slx100-2-fgg484
  set vt = 6
  set vs = "s"
  set ped = TFDD
endif
if ( $design == s6mx ) then
  set part = xc6slx150-3-fgg484
  set vt = 6
  set vs = "s"
  set ped = TFDD
  set area = s6m
endif
if ( $design == p7b ) then
  set part = xc6slx4-2-csg225
  set vt = 6
  set vs = "s"
endif
if ( $design == gps ) then
  set part = xc6slx4-2-csg225
  set vt = 6
  set vs = "s"
endif
if ( $design == gpsx ) then
  set part = xc6slx4-2-cpg196
  set vt = 6
  set vs = "s"
  set area = gps
endif
if ( $design == gpsy ) then
  set part = xcau10p-sbvb484-1-e
  set vt = 8
  set vs = "r"
  set area = gps
endif

# I/O module type
set io = BAD
if ( $sig =~ hh* ) set io = HH
if ( $sig =~ ss* ) set io = SS
if ( $sig =~ dd* ) set io = DD
if ( $sig =~ rr* ) set io = RR
if ( $sig =~ sh* ) set io = SH
if ( $sig =~ dh* ) set io = DH
if ( $sig =~ rh* ) set io = RH
if ( $sig =~ ds* ) set io = DS
if ( $sig =~ st* ) set io = ST
if ( $sig =~ zz* ) set io = ZZ
if ( $sig =~ jj* ) set io = JJ
if ( $sig =~ aa* ) set io = aa
if ( $sig == d )   set io = D
if ( $sig == h )   set io = H
if ( $sig == hx)   set io = HX
if ( $sig == s )   set io = S

# processing engine
set pe = BAD
if ( $sig =~ ?   ) set pe = $ped
if ( $sig =~ ??  ) set pe = $ped
if ( $sig =~ ??r ) set pe = RESAMP
if ( $sig =~ ??n ) set pe = NOOP
if ( $sig =~ ??f ) set pe = FIR
if ( $sig =~ ??q ) set pe = QTFD
if ( $sig =~ ??d ) set pe = DMOD
if ( $sig =~ ??t ) set pe = TFDD
if ( $sig =~ ??u ) set pe = USER
if ( $sig =~ ??w ) set pe = WAVE
if ( $sig =~ ??p ) set pe = PCI
if ( $sig =~ ??rc) set pe = R2C
if ( $sig =~ ??bt) set pe = BOT
if ( $sig =~ ??bx) set pe = BOTX
if ( $sig =~ ??ff) set pe = FFT
if ( $sig =~ ??fx) set pe = FFTX

if ( $?IFUD && $pe != BAD && $sig != ss ) then
  echo "Echo user signature $sig is reserved for ICE default loads"
  exit
endif
if ( $pe == BAD ) then
  set pe = `echo $SIG | awk -F $io '{ print $2 }' `
endif

if ( _$name != _ ) then
  set pe = `echo $name | sed -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/' `
endif

if ( $io == BAD || $pe == BAD ) then
  echo "Unsupported signature: $sig"
  exit
endif

set xsource = 
if ( $pe == FFT || $pe == BOT ) then
##  if ( $design == v6m ) set xsource = coregen/xfft_v8_0.ngc
endif

set toolver = 10
if ( $2 != "sim" ) then

  setenv VIVADO $XILINX/Vivado/2022.2
  setenv VITIS $XILINX/2025.1/Vitis
  #setenv VIVADO $XILINX/Vivado/2023.2

  if ( $?XILINX9 ) then
    setenv XISE $XILINX9
  endif
  if ( $vt >= 3 && $?XILINX11 && $action != "plan" ) then
    setenv XISE $XILINX11
  endif
  if ( $vt >= 3 && $?XILINX12 && $action != "plan" ) then
    setenv XISE $XILINX12
  endif
  if ( $vt >= 3 && $?XILINX13 && $action != "plan" ) then
    setenv XISE $XILINX13
  endif
  if ( $vt >= 4 && $?XILINX14 && $action != "plan" ) then
    setenv XISE $XILINX14
    setenv XIL_PAR_DESIGN_CHECK_VERBOSE 1
  endif
 if ( $?XISE ) then
  if ( -e $XISE/settings64.csh ) then
    source $XISE/settings64.csh
    set toolver = 10
    # new algorithms (-xe=n) bad for V2 and V4
    if ( $vt >= 5 ) set toolver = 12
    if ( $vt >= 6 ) set toolver = 14
    setenv PATH $XISE/ISE/bin/lin64:$PATH
  else if ( -e $XISE/settings.csh ) then
    source $XISE/settings.csh
    set toolver = 9
    setenv XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING 1
  endif
 endif
  #setenv XIL_PAR_NOIORGLLOCCLKSPL 1
  setenv XIL_PAR_ENABLE_LEGALIZER 1
  setenv XIL_PAR_DEBUG_IOCLKPLACER 1
  setenv XIL_DCM_AUTOCALIBRATION_OFF 1
  setenv XIL_MAP_LOCWARN 1
  setenv LIBXCB_ALLOW_SLOPPY_LOCK 1
  setenv XIL_TIMING_ALLOW_IMPOSSIBLE 1
endif

# form the RAM signature to be preprocessed into the top.ucf files RAM INIT_3F
set sver = ( `grep ICE_VERSION $ICEROOT/inc/icelib.h` )
set hver = `printf %08x $sver[3]`
# override version by 8 digit hex number here for 391 jjj
##set hver = 00000187
set hsig = `echo "$SIG  " | od -t x4 -N 4 -A n`
set hdsg = `echo "$design     " | od -t x8 -N 8 -A n`
set hsv  = "$hsig$hver"
set sv1  = "00000000_00000000_00000000_"
set sv2  = "00000000_00000000_00000000_"
if ( $vt >= 5 ) then
  # the values are accessed from an 8bit port to 2 seperate 32 bit BRAMS so must split by words
  set sv1 = "$sv1$hver"
  set sv2 = "$sv2$hsig"
else
  # the values are accessed from an 8bit port to 2 BRAMS so must split by nibbles
  foreach ii ( 2 4 6 8 10 12 14 16 )
    set sv1 = "$sv1`echo $hsv | cut -c $ii`"
  end
  foreach ii ( 1 3 5 7 9 11 13 15 )
    set sv2 = "$sv2`echo $hsv | cut -c $ii`"
  end
endif
set sv0 = "00000000_00000000_${hsig}_${hver}"
set svN = "_00000000_00000000_00000000_00000000"
#echo "hver=$hver. hsig=$hsig. hsv=$hsv. sv1=$sv1. sv2=$sv2."

#echo "/---------------------------------------------------------------------------------------\ "
echo "Xilinx Start act=$action card=$card design=$design area=$area SIG=$SIG IO=$io PE=$pe name=$name seed=$seed "
#echo "\---------------------------------------------------------------------------------------/ "

if ( $action == make & $area == sim ) set action = sim

set chipscope = OFF
set synthesizer = XST
set router = XST
set debug = OFF
set cores = OFF
set source = top.ngc

if ( $action =~ */d ) then
  set action = `echo $action | sed 's/\/d//'`
  set debug = ON
endif
if ( $action =~ */c ) then
  set action = `echo $action | sed 's/\/c//'`
  set cores = ON
endif
if ( $action =~ */o ) then
  set action = `echo $action | sed 's/\/o//'`
  set obf = ON
endif

if ( $action == sim ) then
  set synthesizer = VERILATOR
endif
if ( $action == make/s ) then
  set synthesizer = SYNOPSYS
  set action = make
  set source = tmpsyn/top.edf
  set debug = ON
endif
if ( $action == make/v ) then
  source $VIVADO/settings64.csh
  set synthesizer = VIVADO
  set router = VIVADO
  set action = make
endif
if ( $action == make/q ) then
  set synthesizer = QUARTUS
  set router = QUARTUS
  set action = make
endif
if ( $action == make/x  || $action == smartX ) then
  set debug = ON
  set action = make
  set router = smartX
endif
if ( $debug == ON ) then
  set obf = OFF
endif
set areat = tmp_$$
cd $root/$area

if ( $action == log ) then
  vi ${design}_$sig.logs
endif

if ( $action == clean && -e top.v ) then
  echo " ... clean up old files"
  rm -f top* vivado*.log vivado*.jou
  rm -f post_route.dcp
  rm -f mdefs_user.h
  rm -rf .Xil
  rm -rf .cache
  cp ../lib/vdefs.h .
endif

if ( $action == make  || $action == par || $action == gen ) then
  mkdir -p $root/$areat
#  cp *.h *.v *.sv *.prj *.ucf *.dcp *.xci *.ngc $root/$areat/
  cp * $root/$areat/
  cp $ICEROOT/core/*.sv $ICEROOT/core/*.v $root/$areat/
  if ( $?IFUD ) then
    cd $IFUD
    set list = `ls --hide=nxm`
    cp -r $list $root/$areat/
  endif
  cd $root/$areat
 if ( $router != "QUARTUS" ) then
  rm -f top.ncd
  echo " ... generate the pre-processed top.* files"
  set filen = $area
  if ( -e $design.v ) set filen = $design
  $ICEROOT/jre/ice util vpp  $cwd/$filen.v $cwd/top.v \
	/predefs="{CARD_CPP=$card,IO_CPP=IO_$io,PE_CPP=PE_$pe,HSV_CPP=64'h$hsv,HDSG_CPP=64'h$hdsg}"
  set filen = $area
  if ( -e $design.ucf ) set filen = $design
  $ICEROOT/jre/ice util vpp $cwd/$filen.ucf $cwd/top.ucf \
	/predefs="{$card,IO_$io,PE_$pe,PCI_LANES=$lanes,XTVER=$toolver,${synthesizer}=true,SIGVER=$sv0$svN,SIGVER1=$sv1$svN,SIGVER2=$sv2$svN}" /mdefs=$cwd/mdefs.h
  cp ../opts/fpga.flw .
  set filen = $area
  if ( -e $design.prj ) set filen = $design
  $ICEROOT/jre/ice util vpp $cwd/$filen.prj $cwd/top.prj \
	/predefs="{$card,IO_$io,PE_$pe,PCI_LANES=$lanes,DEBUG_$debug,CORES_$cores,${synthesizer}=true}" /mdefs=$cwd/mdefs.h
  if ( -e topx.prj ) cat topx.prj >> top.prj
  if ( $obf != ON && -e $ICEROOT/code/soc/corez ) then 
    cat top.prj | sed 's/cores/corez/g' > topy.prj 
    mv topy.prj top.prj 
  endif
  cp $root/$areat/top.prj $root/$area/
  cp $root/$areat/top.ucf $root/$area/
  cp $root/$areat/top.v $root/$area/
 endif

  set bbpath = $ICEROOT/code/soc/cores
  if ( $?IFUD ) then
    echo "ICE FPGA User Dir has been set to IFUD=$IFUD"
    set bbpath2 = $IFUD
  else
    set bbpath2 = $ICEROOT/code/soc/$area
  endif
  date
endif

if ( $action == make  && $router == "VIVADO" ) then
  echo " ... running Vivado vflow.tcl script"
  $ICEROOT/jre/ice util ucf2xdc $cwd/top.ucf $cwd/top.xdc
  if ( -e topx.xdc ) cat topx.xdc >> top.xdc
  cp $root/$areat/top.xdc $root/$area/
  vivado -mode tcl -source $root/opts/vflow.tcl -tclargs $part $design $card $io $pe $hsv $obf
  date
  echo "Finished Implement act=$1 design=$design area=$area sig=$sig part=$part"
  cp top.bit $root/$area/
  #cp top.xdc.out $root/$area/
  cp post_route.dcp $root/$area/
  if ( -e top.mcs ) cp top.mcs $root/$area/
  set lfname = $root/$area/${design}_$sig.logs
  grep vFlow vivado.log > $lfname
  grep synth_design vivado.log >> $lfname
  grep opt_design vivado.log >> $lfname
  grep place_design vivado.log >> $lfname
  grep route_design vivado.log >> $lfname
  echo "# timing analysis" >> $lfname
  grep -A 7 "Design Timing" post_route_timing_summary.rpt | grep -A 2 "WNS" >> $lfname
  echo "# utiliation report" >> $lfname
  cat post_place_util.rpt >> $lfname
  echo "# timing report" >> $lfname
  cat post_route_timing_summary.rpt >> $lfname
  cp vivado.log $root/$area/
  $ICEROOT/jre/ice make bits $area ${design}_$sig
  if ( $debug == OFF ) rm -rf $root/$areat
  exit
endif

if ( $action == make  && $router == "QUARTUS" ) then
  echo " ... running Quartus ${design}_setup.tcl script"
  setenv PATH $QUARTUS/quartus/bin:$PATH
  set lfname = $root/$area/${design}_$sig.logs
  echo "Timex ini: `date`" > $lfname
  quartus_sh -t ${design}_setup.tcl
  quartus_ipgenerate --run_default_mode_op $design -c $design
  if ( $design == pic9 || $design == pic9d || $design == pic9p ) then
    # Generation of support logic for F-Tile on Agilex
    quartus_syn --read_settings_files=on --write_settings_files=off $design -c $design --dni --quick_elab
    quartus_tlg --read_settings_files=on --write_settings_files=off --skip_quick_elaboration $design -c $design 
  endif
  echo "Timex syn: `date`" >> $lfname
  quartus_syn --read_settings_files=on --write_settings_files=off $design -c $design
  echo "Timex fit: `date`" >> $lfname
  quartus_fit --read_settings_files=on --write_settings_files=off $design -c $design
  echo "Timex asm: `date`" >> $lfname
  quartus_asm --read_settings_files=on --write_settings_files=off $design -c $design
  quartus_sta $design -c $design --mode=finalize
  echo "Timex sta: `date`" >> $lfname
  cat ${design}.fit.plan.rpt >> $lfname
  cat ${design}.sta.rpt >> $lfname
  grep violated ${design}.sta.rpt >> $lfname
  cat ${design}.fit.summary >> $lfname
  tail $lfname
  if ( $design == pic9 || $design == pic9d || $design == pic9p ) then
    if ( $design == pic9d ) then
      echo " To Program PIC9 on Dev Kit: "
      echo " as root: cd to /board_test_system directory in pic9 folder "
      echo " ./BoardTestSystem.sh (This opens a GUI and initializes the JTAG chain "
      echo "  Close the Board Test System GUI to free the JTAG Chain "
      echo "  Run: "
      echo '  /opt/software/intel/intelFPGA_pro/23.3/quartus/bin/quartus_pgm -m jtag -o "p;pic9.sof" '
    endif
    quartus_pfg -c ${design}.pfg
    cp ${design}.jic $root/$area/${design}_${sig}.jic
    cp ${design}.sof $root/$area/${design}_${sig}.sof
    echo "Copied ${design}.jic and ${design}.sof to $root/$area/"
  else
    quartus_cpf -c ${design}.cof
    cp ${design}.rbf $ICEROOT/xfer/${design}_$sig.rbf
    $ICEROOT/jre/ice make rbf ${design}_$sig $vt
  endif
  if ( $debug == OFF ) rm -rf $root/$areat
  exit

  echo " ... running Quartus qflow.tcl script"
  $ICEROOT/jre/ice util ucf2xdc $cwd/top.ucf $cwd/top.xdc
  cp $root/$areat/top.xdc $root/$area/
  $ALTERA/quartus/bin/quartus_sh -t $root/opts/qflow.tcl $part $design $card $io $pe $hsv
  date
  echo "Finished Implement act=$1 design=$design area=$area sig=$sig part=$part"
  cp top.bit $root/$area
  cp post_route.dcp $root/$area
  set lfname = $root/$area/${design}_$sig.logs
  grep vFlow vivado.log > $lfname
  grep synth_design vivado.log >> $lfname
  grep opt_design vivado.log >> $lfname
  grep place_design vivado.log >> $lfname
  grep route_design vivado.log >> $lfname
  echo "# timing analysis" >> $lfname
  grep -A 7 "Design Timing" post_route_timing_summary.rpt | grep -A 2 "WNS" >> $lfname
  echo "# utiliation report" >> $lfname
  cat post_place_util.rpt >> $lfname
  echo "# timing report" >> $lfname
  cat post_route_timing_summary.rpt >> $lfname
  $ICEROOT/jre/ice make bits $area ${design}_$sig
  if ( $debug == OFF ) rm -rf $root/$areat
  exit
endif

if ( $action == synth || $action == make ) then
  echo " ... synthesize the verilog design: $vs$toolver"
 if ( $synthesizer == SYNOPSYS ) then
  set parts = `echo $part | sed 's/-/ /g'`
  setenv DESIGN $design
  setenv TECH virtex$vt
  setenv PART  `echo $parts | awk '{ print $1 }' `
  setenv SPEED `echo $parts | awk '{ print $2 }' `
  setenv PACK  `echo $parts | awk '{ print $3 }' `
  setenv AREA $area
  if ( $vt == 2 )  setenv TECH virtex2p
  if ( ! -e $design.sdc ) then
    cpp -C -P -DIO_CPP=IO_$io -DPE_CPP=PE_$pe -D$card ../opts/synpro.prj top.prj
    echo "No $design.sdc file found. Use GUI to run Project->ConvertVendorConstraints on top.ucf. Need to Run first."
    touch $design.sdc
    $SYNOPSYS/bin/synplify_pro top.prj
    rm $design.sdc
    if ( ! -e top_conv.sdc ) exit
    cat ../opts/common.sdc  top_conv.sdc > $design.sdc
  endif
  $SYNOPSYS/bin/synplify_pro -batch top.prj
  # cp tmpsyn/synplicity.ucf top.ucf
 endif
 if ( $synthesizer == XST ) then
  xflow -p $part -synth ../opts/synth.opt top.prj
 endif
  date
  echo "Finished Synthesis act=$1 design=$design area=$area sig=$sig part=$part"
endif

if ( $chipscope == ON ) then
  echo " ... apply chipscope modules"
  set insert = $XISE/chipscope/bin/lin/inserter.sh
  if ( ! -e $design.cdc ) $insert -create $design.cdc
  $insert -edit $design.cdc -ngcbuild -i top.ngc top.ngc
endif

if ( $action == par || ( $action == make && -e $source ) ) then
  echo " ... place and route the design: $vs$toolver"
 if ( $router == XST ) then
  xflow -p $part -g seed:$seed -g bbpath:$bbpath -g bbpath2:$bbpath2 -implement ../opts/implement-$vs$toolver.opt $source $xsource
 endif
 if ( $router == smartX ) then
  echo "Running SmartXplorer - in smartx_results..." 
  smartxplorer -p $part -ucf top.ucf -wd smartx_results -l ../smartX_hostlist.txt top.ngc
  echo "Running Timing Analysis - from smartx_results/best_run/..."
  trce -e 20 smartx_results/best_run/top.ncd smartx_results/best_run/top.pcf
  echo "Copying Best Run files to $cwd..."
  cp smartx_results/best_run/top.ncd .
  cp smartx_results/best_run/top_map.map .
  cp smartx_results/best_run/top.par .
  cp smartx_results/best_run/top.twr .
 endif
  date
  echo "Finished Implement act=$1 design=$design area=$area sig=$sig part=$part"
endif

if ( $action == config || ( $action == make && -e top.ncd ) ) then
  echo " ... generate configuration files"
  set bootclk = StartupClk:JtagClk
  if ( $area =~ pic* ) set bootclk = StartupClk:Cclk
  set configfile = config-$vs$vt.opt
  if ( $design =~ pod* && $sig =~ rrn* ) set configfile = config-v4p.opt
  xflow -p $part -g bootclk:$bootclk -config ../opts/$configfile top.ncd
  echo "Finished Configuration act=$1 design=$design area=$area sig=$sig part=$part"
  cp top.ncd $root/$area
  cp top.bit $root/$area
  cat top_map.map top.par top.twr > $root/$area/${design}_$sig.logs
  date
  if ( $debug == OFF ) rm -rf $root/$areat
endif

cd $root/$area

if ( $action == check  || $action == make || $action == par ) then
  grep "used but" top*.*
  grep "timing error" top*.*
endif

if ( $action == install || $action == config || ( $action == make && -e top.bit ) ) then
  echo " ... install Midas files into dat area"
  $ICEROOT/jre/ice make bits $area ${design}_$sig
endif

if ( $action == checkall ) then
 foreach file ( *.logs )
  set vflow = `grep -c vFlow $file`
  if ( $vflow != "0" ) then
   set vscore = `grep -m 1 -A 1 "    -------    " $file`
   set tns = `echo $vscore | awk '{ print $14 }' `
   set ths = `echo $vscore | awk '{ print $18 }' `
   set tps = `echo $vscore | awk '{ print $22 }' `
   set syn = `grep "synth_design:" $file | awk '{ print $10 }' `
   set plc = `grep "place_design:" $file | awk '{ print $10 }' `
   set rte = `grep "route_design:" $file | awk '{ print $10 }' `
   set date = `cat $file | grep -m 1 "Date"  | awk -F ' : ' '{ print $2 }' `
   echo "  $file    $date   Score (Setup: $tns, Hold: $ths, Pulse: $tps)   SYN: $syn  PAR: $plc $rte" 
  else
   set score = `cat $file | grep "Timing Score" | sed 's/Timing//' | sed 's/Component Switching //'`
   set map   = `cat $file | grep "REAL time to MAP" | awk -F : '{ print $2 }' `
   set comp  = `cat $file | grep "REAL time to PAR" | awk -F : '{ print $2 }' `
   set date  = `cat $file | grep -m 1 "Date"  | awk -F ' : ' '{ print $2 }' `
   echo "  $file     $date    $score    MAP: $map    PAR: $comp" 
   grep "used but" $file
  endif
 end
endif

if ( $action == edit ) then
  fpga_editor top.ncd &
endif
if ( $action == edit/v ) then
  source $VIVADO/settings64.csh
  vivado -mode tcl -source $root/opts/vedit.tcl &
endif

if ( $action == power ) then
  xpa top.ncd
endif

if ( $action == plan ) then
  floorplanner top.ngd &
endif

if ( $action == timing ) then
  timingan top_map.ncd &
endif

if ( $action == ise ) then
  ise &
endif

if ( $action == vivado ) then
  source $VIVADO/settings64.csh
  vivado &
endif

if ( $action == vitis ) then
  source $VITIS/settings64.csh
  vitis &
endif

if ( $action == impact ) then
  impact &
endif

if ( $action == core || $action == coregen ) then
  # coregen output must be in $area for edifs to be found
  if ( -e coregen.cgp ) then
    coregen -p coregen.cgp
  else
    coregen 
  endif
endif

if ( $action == sim ) then
  mkdir -p $root/$areat 
  cp * $root/$areat
  cp $ICEROOT/core/*.sv $ICEROOT/core/*.v $root/$areat/
  if ( $?IFUD ) then
    cp -r $IFUD/* $root/$areat/
  endif
  cd $root/$areat
  set pe = $name
  echo "Verilating top.args for name=$name IFUD=$IFUD"
  $ICEROOT/jre/ice util vpp  $cwd/sim.v $cwd/top.v /predefs="{IO_CPP=IO_$io,PE_CPP=PE_$pe}" /mdefs=$cwd/mdefs.h
  $ICEROOT/jre/ice util vpp  $cwd/sim.args $cwd/top.args /predefs="{IO_CPP=IO_$io,PE_CPP=PE_$pe}" /mdefs=$cwd/mdefs.h
  cp top.v $root/$area/
  cp top.v core.v
  rm -rf obj_dir 
  set barch = 64
  if ( -e topx.args ) cat topx.args >> top.args
  if ( $obf != ON && -e $ICEROOT/code/soc/corez ) then 
    cat top.args | sed 's/cores/corez/g' > topy.args 
    mv topy.args top.args 
  endif
  verilator -j 8 -f top.args
  echo "Compiling top.args for name=$name IFUD=$IFUD"
  cc -shared -fPIC -o libVCore.so -I$VERILATOR_ROOT/include -I$ICEROOT/inc -Iobj_dir -DIO_$io -DPE_$pe \
    libVCore.cpp obj_dir/*.cpp $VERILATOR_ROOT/include/verilated.cpp $VERILATOR_ROOT/include/verilated_vcd_c.cpp -lstdc++
  if ( _$name != _ ) then
    cp libVCore.so $ICEROOT/core/libHOC\$VHS_lin$barch.so
    if ( $seed == spice ) then
      mv libVCore.so $IFUD/core/lib$name\$VHS_lin$barch.so
    else
      mv libVCore.so $NMROOT/nxm/$seed/core/lib$name\$VHS_lin$barch.so
    endif
  else
    mv libVCore.so $ICEROOT/lib/libVCore_lin$barch.so
    $ICEROOT/jre/ice build VCore lib ice
  endif
  if ( $debug == OFF ) rm -rf $root/$areat
endif

