/**********************************************

 ICE Proprietary Software - do NOT disseminate

All procedures and scripts contained in this tree are ICE 
proprietary software and must not be used outside of this effort.

If this directory contains the /com or /pic# subdirectories,
the effort is defined in the non-disclosure agreement you must 
have signed to be reading this file.  If this release contains only
the /lib, /opts, /cores, and processor module subdirectories, 
a verbal agreement is sufficient.  

If this is not the case, you and the person who released it to you 
are in violation of such agreement and are responsible for any 
damages incurred, both legal and financial.

**********************************************/

These scripts depend on the C shell and three environment variables:

  $XILINX   the root of the Xilinx ISE installation (ie /user/opt/Xilinx)
  $VIVADO   the root of the VIVADO installation (ie /user/opt/Xilinx/Vivado/2019.2)
  $ICEROOT  the root of the ICE option tree (ie /user/opt/icexxx)

The System-On-Chip code is distributed as iceXXX-YY-soc.zip.
The soc subdirectory should reside in the directory $ICEROOT/code .
With this done, NeXtMidas can be used to Midasize the Xilinx bit files.
The $ICEROOT/code/soc/xilinx script bypasses the ISE|VIVADO gui.
Since we do not use the ISE|VIVADO gui, we do not have any project files.
If you choose to use the gui, you will need to match the settings defined in 
the scripts found in the $ICEROOT/code/soc/opts directory, xflow for ISE, 
or vflow for VIVADO.

To compile a load for the PIC5, run:

  $ICEROOT/code/soc/xilinx make pic5 ssu

where ss is for single ended I/O modules, or

  $ICEROOT/code/soc/xilinx make pic5 hhu

where hh is for hypertransport I/O modules.  The u causes the PE_USER define
to select the user defined processing core in soc/lib/userengine.v .  

The combined string ssu or hhu is called the signature.
You can either replace this userengine.v file, or change 
the soc/lib/pic5.prj file to point to your own directory.  


Similarly, to compile a load for the DTDM;

  $ICEROOT/code/soc/xilinx make dtdm ssu

where ss is for processor modules on PIC4X cards, or

  $ICEROOT/code/soc/xilinx make dtdm hhu

where hh is for processor modules on PIC5+ cards, or

  $ICEROOT/code/soc/xilinx make/v k8m rru

where rr is for processor modules on PIC8+ cards.


Similarly, to compile a load for the V6M;

  $ICEROOT/code/soc/xilinx make v6m hhu

Similarly, to compile a load for the K8M;

  $ICEROOT/code/soc/xilinx make/v k8m rru

Similarly, to compile a load for the K8P;

  $ICEROOT/code/soc/xilinx make/v k8p rru

The K8M|K8P are only supported on PIC8+ cards.


Xilinx GUI users:

If you use the ISE GUI to compile, you will still first need to run:

  $ICEROOT/code/soc/xilinx gen k8m rru

with the proper signature to preprocess k8m.v and k8m.ucf into 
a top.v and top.xdc that can be used by the ISE|VIVADO.

After a successful compile, the .bit files need to be Midasized for the ICE libraries.

To convert the bit files to Midas files, run:

  nm pic make bits k8m rru

with the proper configuration signature.  This puts the output files in $ICEROOT/dat.

For the K8M, run:

  $ICEROOT/code/soc/xilinx gen k8m rru

  <the VIVADO compile>

  nm pic make bits k8m k8m_rru

with the proper configuration signature.


VHDL users:

All ICE functions are written in verilog.  
Do not change the top level verilog files.
If your core uses VHDL code, use the userengine.v verilog file to call function modules in vhdl.
If your core requires other verilog or vhdl files, they must be added to the <card>.prj file.

