# puts "vFlow part=$part design=$desn card=$card io=$io pe=$pe hsv=$hsv obf=$obf"
vFlow part=xcku040-fbva900-2-i design=k8m card=K8M io=RR pe=DM8 hsv=4d4452520000018f obf=OFF
#   puts "vFlow read file=$fn base=$bn"
vFlow read file=top.v base=top.v
vFlow read file=sysclocks.v base=sysclocks.v
vFlow read file=../lib/bscanif.v base=bscanif.v
vFlow read file=../lib/registers.v base=registers.v
vFlow read file=../lib/rams.v base=rams.v
vFlow read file=../lib/muxes.v base=muxes.v
vFlow read file=../lib/buffers.v base=buffers.v
vFlow read file=../lib/processor.v base=processor.v
vFlow read file=../lib/testport.v base=testport.v
vFlow read file=../lib/sdram4x.v base=sdram4x.v
vFlow read file=../lib/auxiliary.v base=auxiliary.v
vFlow read file=../lib/dmacontroller.v base=dmacontroller.v
vFlow read file=../lib/hyperlink.v base=hyperlink.v
vFlow read file=../lib/mcengine.v base=mcengine.v
vFlow read file=../lib/outadder.sv base=outadder.sv
vFlow read file=../lib/nullengine.v base=nullengine.v
vFlow read file=../lib/noopengine.v base=noopengine.v
vFlow read file=../lib/converts.v base=converts.v
vFlow read file=../k8xip/k8mig/mig_0.xci base=mig_0.xci
vFlow read file=../k8xip/gtwiz/*.v base=*.v
vFlow read file=../k8xip/k8rio/*.v base=*.v
vFlow read file=../k8xip/riop8.v base=riop8.v
vFlow read file=../com/pcie_lc_v8_src.g3x4.rp/*.v base=*.v
vFlow read file=../k8xip/riop8nv.v base=riop8nv.v
vFlow read file=../lib/coretypes.sv base=coretypes.sv
vFlow read file=../lib/corefuncs.sv base=corefuncs.sv
vFlow read file=../lib/coretasks.sv base=coretasks.sv
vFlow read file=../corez/corecomps.sv base=corecomps.sv
vFlow read file=RFP.sv base=RFP.sv
vFlow read file=AWG.sv base=AWG.sv
vFlow read file=MOD.sv base=MOD.sv
vFlow read file=LRS.sv base=LRS.sv
vFlow read file=DUC.sv base=DUC.sv
vFlow read file=UDAT.sv base=UDAT.sv
vFlow read file=UDUC.sv base=UDUC.sv
vFlow read file=Noop.sv base=Noop.sv
vFlow read file=../corez/jvmengine.v base=jvmengine.v
vFlow read file=../corez/tfddengine.v base=tfddengine.v
vFlow read file=../corez/ddsengine.v base=ddsengine.v
vFlow read file=../corez/cicengine.v base=cicengine.v
vFlow read file=../corez/firengine.v base=firengine.v
vFlow read file=../corez/resengine.v base=resengine.v
vFlow read file=../corez/botengine.v base=botengine.v
vFlow read file=../corez/r2cengine.v base=r2cengine.v
vFlow read file=../lib/viterbi.v base=viterbi.v
vFlow read file=../k8xip/k8vit/viterbi_v27.v base=viterbi_v27.v
vFlow read file=../k8xip/k8vit/viterbi_v27.dcp base=viterbi_v27.dcp
vFlow read file=../k8xip/riop8n.v base=riop8n.v
vFlow read file=../k8xip/icetge.v base=icetge.v
vFlow read file=../k8xip/k8tge/*.v base=*.v
vFlow read file=../corez/pktengine.v base=pktengine.v
vFlow read file=PKT2DAT.sv base=PKT2DAT.sv
vFlow read file=IQAGC.sv base=IQAGC.sv
vFlow read file=IQSSR.sv base=IQSSR.sv
vFlow read file=IQMMA.sv base=IQMMA.sv
vFlow read file=IQMMAX.sv base=IQMMAX.sv
vFlow read file=IQKMM.sv base=IQKMM.sv
vFlow read file=IQDDC.sv base=IQDDC.sv
vFlow read file=IQSDF.sv base=IQSDF.sv
vFlow read file=IQRFP.sv base=IQRFP.sv
vFlow read file=IQUWB.sv base=IQUWB.sv
vFlow read file=DMOD.sv base=DMOD.sv
vFlow read file=MODM.sv base=MODM.sv
vFlow read file=Filters.sv base=Filters.sv
vFlow read file=Modems.sv base=Modems.sv
# puts "vFlow finished part=$part design=$desn card=$card io=$io p2=$pe hsv=$hsv"
vFlow finished part=xcku040-fbva900-2-i design=k8m card=K8M io=RR p2=DM8 hsv=4d4452520000018f
# synth_design -top top -part $part -include_dirs ../lib -verilog_define VIVADO=true -keep_equivalent_registers
Command: synth_design -top top -part xcku040-fbva900-2-i -include_dirs ../lib -verilog_define VIVADO=true -keep_equivalent_registers
Starting synth_design
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
synth_design completed successfully
synth_design: Time (s): cpu = 00:32:22 ; elapsed = 00:29:12 . Memory (MB): peak = 7843.352 ; gain = 6314.359 ; free physical = 41647 ; free virtual = 65308
# opt_design
Command: opt_design
Running DRC as a precondition to command opt_design
INFO: [Opt 31-1021] In phase Retarget, 85 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
INFO: [Opt 31-1021] In phase Constant propagation, 84 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
Resolution: If this is not expected, please check for DONT_TOUCH properties or timing constraint set on the empty box cell or on nets connected to the cell. If found, remove the relevant DONT_TOUCH property or timing constraint and re-run opt_design.
INFO: [Opt 31-1021] In phase Sweep, 2999 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
INFO: [Opt 31-1021] In phase BUFG optimization, 3 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
INFO: [Opt 31-1021] In phase Post Processing Netlist, 321 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
opt_design completed successfully
opt_design: Time (s): cpu = 00:35:17 ; elapsed = 00:18:52 . Memory (MB): peak = 9844.566 ; gain = 1937.184 ; free physical = 40761 ; free virtual = 64776
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
WARNING: [Opt 31-1090] MMCM/PLL sc/f_dcm has compensation set to INTERNAL but has net connected from CLKFBOUT to CLKFBIN. Mandatory logic optimization has attempted to trim the net, but a LOC assignment on the MMCM/PLL prevents the optimization. Please remove the LOC assignment on the MMCM/PLL or use the disconnect_net TCL command to trim the net prior to place_design.
WARNING: [Opt 31-1090] MMCM/PLL sc/o_dcm has compensation set to INTERNAL but has net connected from CLKFBOUT to CLKFBIN. Mandatory logic optimization has attempted to trim the net, but a LOC assignment on the MMCM/PLL prevents the optimization. Please remove the LOC assignment on the MMCM/PLL or use the disconnect_net TCL command to trim the net prior to place_design.
WARNING: [Opt 31-1090] MMCM/PLL sc/f_dcm has compensation set to INTERNAL but has net connected from CLKFBOUT to CLKFBIN. Mandatory logic optimization has attempted to trim the net, but a LOC assignment on the MMCM/PLL prevents the optimization. Please remove the LOC assignment on the MMCM/PLL or use the disconnect_net TCL command to trim the net prior to place_design.
# place_design
Command: place_design
Running DRC as a precondition to command place_design
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
place_design completed successfully
place_design: Time (s): cpu = 01:10:39 ; elapsed = 00:36:25 . Memory (MB): peak = 9844.566 ; gain = 0.000 ; free physical = 38330 ; free virtual = 62590
# route_design 
Command: route_design
Running DRC as a precondition to command route_design
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
route_design completed successfully
route_design: Time (s): cpu = 01:05:22 ; elapsed = 00:27:36 . Memory (MB): peak = 9844.566 ; gain = 0.000 ; free physical = 37365 ; free virtual = 61899
# timing analysis
    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.048        0.000                      0               581375        0.016        0.000                      0               580707        0.000        0.000                       0                197202  
# utiliation report
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
| Date         : Thu Oct 16 20:21:58 2025
| Host         : fedora running 64-bit unknown
| Command      : report_utilization -file post_place_util.rpt
| Design       : top
| Device       : xcku040-fbva900-2-i
| Speed File   : -2
| Design State : Fully Placed
------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. CLB Logic Distribution
3. BLOCKRAM
4. ARITHMETIC
5. I/O
6. CLOCK
7. ADVANCED
8. CONFIGURATION
9. Primitives
10. Black Boxes
11. Instantiated Netlists

1. CLB Logic
------------

+----------------------------+--------+-------+------------+-----------+-------+
|          Site Type         |  Used  | Fixed | Prohibited | Available | Util% |
+----------------------------+--------+-------+------------+-----------+-------+
| CLB LUTs                   | 163873 |     0 |          0 |    242400 | 67.60 |
|   LUT as Logic             | 131290 |     0 |          0 |    242400 | 54.16 |
|   LUT as Memory            |  32583 |     0 |          0 |    112800 | 28.89 |
|     LUT as Distributed RAM |  14349 |     0 |            |           |       |
|     LUT as Shift Register  |  18234 |     0 |            |           |       |
| CLB Registers              | 151890 |     0 |          0 |    484800 | 31.33 |
|   Register as Flip Flop    | 151889 |     0 |          0 |    484800 | 31.33 |
|   Register as Latch        |      0 |     0 |          0 |    484800 |  0.00 |
|   Register as AND/OR       |      1 |     0 |          0 |    484800 | <0.01 |
| CARRY8                     |   6536 |     0 |          0 |     30300 | 21.57 |
| F7 Muxes                   |   3395 |     0 |          0 |    121200 |  2.80 |
| F8 Muxes                   |     64 |     0 |          0 |     60600 |  0.11 |
| F9 Muxes                   |      0 |     0 |          0 |     30300 |  0.00 |
+----------------------------+--------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining.


1.1 Summary of Registers by Type
--------------------------------

+--------+--------------+-------------+--------------+
|  Total | Clock Enable | Synchronous | Asynchronous |
+--------+--------------+-------------+--------------+
| 1      |            _ |           - |            - |
| 0      |            _ |           - |          Set |
| 0      |            _ |           - |        Reset |
| 0      |            _ |         Set |            - |
| 0      |            _ |       Reset |            - |
| 0      |          Yes |           - |            - |
| 509    |          Yes |           - |          Set |
| 2359   |          Yes |           - |        Reset |
| 2292   |          Yes |         Set |            - |
| 146729 |          Yes |       Reset |            - |
+--------+--------------+-------------+--------------+


2. CLB Logic Distribution
-------------------------

+--------------------------------------------+--------+-------+------------+-----------+-------+
|                  Site Type                 |  Used  | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+--------+-------+------------+-----------+-------+
| CLB                                        |  27055 |     0 |          0 |     30300 | 89.29 |
|   CLBL                                     |  13992 |     0 |            |           |       |
|   CLBM                                     |  13063 |     0 |            |           |       |
| LUT as Logic                               | 131290 |     0 |          0 |    242400 | 54.16 |
|   using O5 output only                     |   1627 |       |            |           |       |
|   using O6 output only                     | 100375 |       |            |           |       |
|   using O5 and O6                          |  29288 |       |            |           |       |
| LUT as Memory                              |  32583 |     0 |          0 |    112800 | 28.89 |
|   LUT as Distributed RAM                   |  14349 |     0 |            |           |       |
|     using O5 output only                   |      0 |       |            |           |       |
|     using O6 output only                   |   4879 |       |            |           |       |
|     using O5 and O6                        |   9470 |       |            |           |       |
|   LUT as Shift Register                    |  18234 |     0 |            |           |       |
|     using O5 output only                   |      0 |       |            |           |       |
|     using O6 output only                   |  17295 |       |            |           |       |
|     using O5 and O6                        |    939 |       |            |           |       |
| CLB Registers                              | 151890 |     0 |          0 |    484800 | 31.33 |
|   Register driven from within the CLB      |  89873 |       |            |           |       |
|   Register driven from outside the CLB     |  62017 |       |            |           |       |
|     LUT in front of the register is unused |  34123 |       |            |           |       |
|     LUT in front of the register is used   |  27894 |       |            |           |       |
| Unique Control Sets                        |   5396 |       |          0 |     60600 |  8.90 |
+--------------------------------------------+--------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slices * 2, Review the Control Sets Report for more information regarding control sets.


3. BLOCKRAM
-----------

+-------------------+-------+-------+------------+-----------+-------+
|     Site Type     |  Used | Fixed | Prohibited | Available | Util% |
+-------------------+-------+-------+------------+-----------+-------+
| Block RAM Tile    | 497.5 |     0 |          0 |       600 | 82.92 |
|   RAMB36/FIFO*    |   395 |     0 |          0 |       600 | 65.83 |
|     RAMB36E2 only |   395 |       |            |           |       |
|   RAMB18          |   205 |     0 |          0 |      1200 | 17.08 |
|     RAMB18E2 only |   205 |       |            |           |       |
+-------------------+-------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2


4. ARITHMETIC
-------------

+----------------+------+-------+------------+-----------+-------+
|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| DSPs           | 1678 |     0 |          0 |      1920 | 87.40 |
|   DSP48E2 only | 1678 |       |            |           |       |
+----------------+------+-------+------------+-----------+-------+


5. I/O
------

+------------------+------+-------+------------+-----------+-------+
|     Site Type    | Used | Fixed | Prohibited | Available | Util% |
+------------------+------+-------+------------+-----------+-------+
| Bonded IOB       |  140 |   132 |          0 |       468 | 29.91 |
| HPIOB            |  126 |   118 |          0 |       364 | 34.62 |
|   INPUT          |    3 |       |            |           |       |
|   OUTPUT         |   33 |       |            |           |       |
|   BIDIR          |   90 |       |            |           |       |
| HRIO             |   14 |    14 |          0 |       104 | 13.46 |
|   INPUT          |    4 |       |            |           |       |
|   OUTPUT         |    2 |       |            |           |       |
|   BIDIR          |    8 |       |            |           |       |
| HPIOBDIFFINBUF   |    9 |     9 |          0 |       192 |  4.69 |
|   DIFFINBUF      |    9 |     9 |            |           |       |
| HPIOBDIFFOUTBUF  |    0 |     0 |          0 |       192 |  0.00 |
| HRIODIFFINBUF    |    0 |     0 |          0 |        48 |  0.00 |
| HRIODIFFOUTBUF   |    0 |     0 |          0 |        48 |  0.00 |
| BITSLICE_CONTROL |   21 |     0 |          0 |        80 | 26.25 |
| BITSLICE_RX_TX   |  105 |   105 |          0 |      3120 |  3.37 |
|   RXTX_BITSLICE  |  105 |   105 |            |           |       |
| BITSLICE_TX      |   21 |     0 |          0 |        80 | 26.25 |
| RIU_OR           |   11 |     0 |          0 |        40 | 27.50 |
+------------------+------+-------+------------+-----------+-------+


6. CLOCK
--------

+----------------------+------+-------+------------+-----------+-------+
|       Site Type      | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs |   27 |     2 |          0 |       480 |  5.63 |
|   BUFGCE             |   11 |     0 |          0 |       240 |  4.58 |
|   BUFGCE_DIV         |    2 |     2 |          0 |        40 |  5.00 |
|   BUFG_GT            |   14 |     0 |          0 |       120 | 11.67 |
|   BUFGCTRL*          |    0 |     0 |          0 |        80 |  0.00 |
| PLLE3_ADV            |    3 |     0 |          0 |        20 | 15.00 |
| MMCME3_ADV           |    3 |     3 |          0 |        10 | 30.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.


7. ADVANCED
-----------

+-----------------+------+-------+------------+-----------+-------+
|    Site Type    | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| GTHE3_CHANNEL   |   12 |    12 |          0 |        16 | 75.00 |
| GTHE3_COMMON    |    3 |     0 |          0 |         4 | 75.00 |
| IBUFDS_GTE3     |    3 |     3 |          0 |         8 | 37.50 |
| OBUFDS_GTE3     |    0 |     0 |          0 |         8 |  0.00 |
| OBUFDS_GTE3_ADV |    0 |     0 |          0 |         8 |  0.00 |
| PCIE_3_1        |    1 |     1 |          0 |         3 | 33.33 |
| SYSMONE1        |    0 |     0 |          0 |         1 |  0.00 |
+-----------------+------+-------+------------+-----------+-------+


8. CONFIGURATION
----------------

+-------------+------+-------+------------+-----------+--------+
|  Site Type  | Used | Fixed | Prohibited | Available |  Util% |
+-------------+------+-------+------------+-----------+--------+
| BSCANE2     |    3 |     0 |          0 |         4 |  75.00 |
| DNA_PORTE2  |    0 |     0 |          0 |         1 |   0.00 |
| EFUSE_USR   |    0 |     0 |          0 |         1 |   0.00 |
| FRAME_ECCE3 |    0 |     0 |          0 |         1 |   0.00 |
| ICAPE3      |    1 |     0 |          0 |         2 |  50.00 |
| MASTER_JTAG |    0 |     0 |          0 |         1 |   0.00 |
| STARTUPE3   |    1 |     0 |          0 |         1 | 100.00 |
+-------------+------+-------+------------+-----------+--------+


9. Primitives
-------------

+------------------+--------+---------------------+
|     Ref Name     |  Used  | Functional Category |
+------------------+--------+---------------------+
| FDRE             | 146729 |            Register |
| LUT2             |  45068 |                 CLB |
| LUT6             |  42157 |                 CLB |
| LUT3             |  28559 |                 CLB |
| LUT4             |  24100 |                 CLB |
| RAMD32           |  18484 |                 CLB |
| LUT5             |  16184 |                 CLB |
| SRLC32E          |  14961 |                 CLB |
| CARRY8           |   6536 |                 CLB |
| LUT1             |   4510 |                 CLB |
| SRL16E           |   4212 |                 CLB |
| RAMD64E          |   3840 |                 CLB |
| MUXF7            |   3395 |                 CLB |
| FDCE             |   2359 |            Register |
| FDSE             |   2292 |            Register |
| DSP48E2          |   1678 |          Arithmetic |
| RAMS32           |   1487 |                 CLB |
| FDPE             |    509 |            Register |
| RAMB36E2         |    395 |            BLOCKRAM |
| RAMB18E2         |    205 |            BLOCKRAM |
| RXTX_BITSLICE    |    105 |                 I/O |
| IBUFCTRL         |     86 |              Others |
| INBUF            |     77 |                 I/O |
| OBUFT_DCIEN      |     72 |                 I/O |
| MUXF8            |     64 |                 CLB |
| OBUFT            |     32 |                 I/O |
| OBUF             |     29 |                 I/O |
| TX_BITSLICE_TRI  |     21 |                 I/O |
| BITSLICE_CONTROL |     21 |                 I/O |
| BUFG_GT          |     14 |               Clock |
| GTHE3_CHANNEL    |     12 |            Advanced |
| RIU_OR           |     11 |                 I/O |
| BUFG_GT_SYNC     |     11 |               Clock |
| BUFGCE           |     11 |               Clock |
| INV              |      9 |                 CLB |
| DIFFINBUF        |      9 |                 I/O |
| RAMS64E          |      8 |                 CLB |
| HPIO_VREF        |      8 |                 I/O |
| PLLE3_ADV        |      3 |               Clock |
| MMCME3_ADV       |      3 |               Clock |
| IBUFDS_GTE3      |      3 |            Advanced |
| GTHE3_COMMON     |      3 |            Advanced |
| BSCANE2          |      3 |       Configuration |
| BUFGCE_DIV       |      2 |               Clock |
| STARTUPE3        |      1 |       Configuration |
| PCIE_3_1         |      1 |            Advanced |
| ICAPE3           |      1 |       Configuration |
| AND2B1L          |      1 |              Others |
+------------------+--------+---------------------+


10. Black Boxes
---------------

+----------------------------+------+
|          Ref Name          | Used |
+----------------------------+------+
| tge_0_ff_synchronizer_680  |    1 |
| tge_0_ff_synchronizer_360  |    1 |
| tge_0_ff_synchronizer_1586 |    1 |
| tge_0_ff_synchronizer_1133 |    1 |
+----------------------------+------+


11. Instantiated Netlists
-------------------------

+-------------+------+
|   Ref Name  | Used |
+-------------+------+
| viterbi_v27 |    8 |
| mig_0_phy   |    1 |
| mig_0       |    1 |
| dbg_hub     |    1 |
+-------------+------+


# timing report
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
| Date              : Thu Oct 16 20:57:13 2025
| Host              : fedora running 64-bit unknown
| Command           : report_timing_summary -file post_route_timing_summary.rpt
| Design            : top
| Device            : xcku040-fbva900
| Speed File        : -2  PRODUCTION 1.25 12-04-2018
| Temperature Grade : I
-----------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (5)
6. checking no_output_delay (11)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (5)
------------------------------
 There are 5 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (11)
--------------------------------
 There are 11 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.048        0.000                      0               581375        0.016        0.000                      0               580707        0.000        0.000                       0                197202  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                                                                                       Waveform(ns)           Period(ns)      Frequency(MHz)
-----                                                                                       ------------           ----------      --------------
cclkp                                                                                       {0.000 1.666}          3.333           300.030         
  mmcm_clkout0                                                                              {0.000 2.000}          4.000           250.025         
    pll_clk[0]                                                                              {0.000 0.250}          0.500           2000.200        
      pll_clk[0]_DIV                                                                        {0.000 2.000}          4.000           250.025         
    pll_clk[1]                                                                              {0.000 0.250}          0.500           2000.200        
      pll_clk[1]_DIV                                                                        {0.000 2.000}          4.000           250.025         
    pll_clk[2]                                                                              {0.000 0.250}          0.500           2000.200        
      pll_clk[2]_DIV                                                                        {0.000 2.000}          4.000           250.025         
  mmcm_clkout6                                                                              {0.000 4.000}          7.999           125.013         
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {0.000 16.500}         33.000          30.303          
drck1                                                                                       {0.000 10.000}         20.000          50.000          
drck2                                                                                       {0.000 10.000}         20.000          50.000          
pclkp                                                                                       {0.000 5.000}          10.000          100.000         
  GTHE3_CHANNEL_QPLL1CLK[0]                                                                 {0.000 0.100}          0.200           5000.001        
  GTHE3_CHANNEL_QPLL1REFCLK[0]                                                              {0.000 5.000}          10.000          100.000         
  txoutclk_out[0]_1                                                                         {0.000 1.000}          2.000           500.000         
    genblk1[0].user_clk_1                                                                   {0.000 2.000}          4.000           250.000         
    mcap_clk_1                                                                              {0.000 4.000}          8.000           125.000         
    pipe_clk_1                                                                              {0.000 2.000}          4.000           250.000         
qclkp                                                                                       {0.000 5.000}          10.000          100.000         
  f_fb                                                                                      {0.000 5.000}          10.000          100.000         
  gclkf                                                                                     {0.000 3.000}          6.000           166.667         
  gclkf2                                                                                    {0.000 1.500}          3.000           333.333         
  gclkv                                                                                     {0.000 1.250}          2.500           400.000         
  gclkx                                                                                     {0.000 2.083}          4.167           240.000         
  gclky                                                                                     {0.000 2.500}          5.000           200.000         
    gclks                                                                                   {0.000 5.000}          10.000          100.000         
  lclks                                                                                     {0.000 5.000}          10.000          100.000         
  lclkz                                                                                     {0.000 1.667}          3.333           300.000         
rclkp                                                                                       {0.000 3.200}          6.400           156.250         
  GTHE3_CHANNEL_QPLL0CLK[0]                                                                 {0.000 0.067}          0.133           7499.999        
    GTHE3_CHANNEL_RXOUTCLK[0]                                                               {0.000 2.133}          4.267           234.375         
    GTHE3_CHANNEL_TXOUTCLK[0]                                                               {0.000 2.133}          4.267           234.375         
  GTHE3_CHANNEL_QPLL0REFCLK[0]                                                              {0.000 3.200}          6.400           156.250         
  genblk2[0].qpll0outclk                                                                    {0.000 0.097}          0.194           5156.250        
    gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                   {0.000 1.600}          3.200           312.500         
    rxoutclk                                                                                {0.000 1.600}          3.200           312.500         
    rxoutclk_1                                                                              {0.000 1.600}          3.200           312.500         
    rxoutclk_2                                                                              {0.000 1.600}          3.200           312.500         
    rxoutclk_3                                                                              {0.000 1.600}          3.200           312.500         
  genblk2[0].qpll0outrefclk                                                                 {0.000 3.200}          6.400           156.250         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                                           WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                                                           -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
cclkp                                                                                             1.727        0.000                      0                   23        0.056        0.000                      0                   23        0.500        0.000                       0                    19  
  mmcm_clkout0                                                                                    0.309        0.000                      0                15848        0.030        0.000                      0                15848        0.600        0.000                       0                  9658  
    pll_clk[0]                                                                                                                                                                                                                                0.072        0.000                       0                     9  
      pll_clk[0]_DIV                                                                                                                                                                                                                          0.578        0.000                       0                    40  
    pll_clk[1]                                                                                                                                                                                                                                0.072        0.000                       0                     9  
      pll_clk[1]_DIV                                                                                                                                                                                                                          0.578        0.000                       0                    40  
    pll_clk[2]                                                                                                                                                                                                                                0.072        0.000                       0                     6  
      pll_clk[2]_DIV                                                                                                                                                                                                                          0.578        0.000                       0                    25  
  mmcm_clkout6                                                                                    1.791        0.000                      0                 5618        0.040        0.000                      0                 5156        0.804        0.000                       0                  1728  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK       29.707        0.000                      0                  910        0.032        0.000                      0                  910       15.832        0.000                       0                   479  
drck1                                                                                            19.609        0.000                      0                    1        0.119        0.000                      0                    1        9.725        0.000                       0                     2  
drck2                                                                                            15.471        0.000                      0                  547        0.034        0.000                      0                  547        9.146        0.000                       0                   256  
pclkp                                                                                             8.472        0.000                      0                  118        0.041        0.000                      0                  118        4.442        0.000                       0                   144  
  txoutclk_out[0]_1                                                                               0.194        0.000                      0                 1172        0.031        0.000                      0                 1172        0.000        0.000                       0                    37  
    genblk1[0].user_clk_1                                                                         0.048        0.000                      0                 2953        0.031        0.000                      0                 2953        0.000        0.000                       0                   722  
    mcap_clk_1                                                                                                                                                                                                                                0.000        0.000                       0                     1  
    pipe_clk_1                                                                                    0.538        0.000                      0                 2026        0.031        0.000                      0                 2026        0.000        0.000                       0                  1126  
qclkp                                                                                             9.399        0.000                      0                    1        0.132        0.000                      0                    1        2.000        0.000                       0                     6  
  f_fb                                                                                                                                                                                                                                        8.929        0.000                       0                     2  
  gclkf                                                                                           0.149        0.000                      0               495912        0.016        0.000                      0               495912        2.020        0.000                       0                158099  
  gclkf2                                                                                                                                                                                                                                      1.621        0.000                       0                     2  
  gclkv                                                                                                                                                                                                                                       1.121        0.000                       0                     2  
  gclkx                                                                                           0.217        0.000                      0                12099        0.030        0.000                      0                12099        1.229        0.000                       0                  5568  
  gclky                                                                                           0.382        0.000                      0                 1348        0.032        0.000                      0                 1348        1.646        0.000                       0                   447  
    gclks                                                                                         3.664        0.000                      0                 3815        0.033        0.000                      0                 3815        2.725        0.000                       0                  1972  
  lclks                                                                                           3.980        0.000                      0                  849        0.055        0.000                      0                  849        4.332        0.000                       0                   583  
  lclkz                                                                                                                                                                                                                                       1.954        0.000                       0                     2  
rclkp                                                                                             4.586        0.000                      0                  678        0.036        0.000                      0                  678        2.925        0.000                       0                   584  
    GTHE3_CHANNEL_RXOUTCLK[0]                                                                     0.271        0.000                      0                 1986        0.033        0.000                      0                 1986        0.486        0.000                       0                  1056  
    GTHE3_CHANNEL_TXOUTCLK[0]                                                                     0.304        0.000                      0                 1142        0.038        0.000                      0                 1142        0.486        0.000                       0                   634  
    gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                         0.086        0.000                      0                19851        0.030        0.000                      0                19851        0.471        0.000                       0                  9736  
    rxoutclk                                                                                      0.297        0.000                      0                 2277        0.036        0.000                      0                 2277        0.486        0.000                       0                  1052  
    rxoutclk_1                                                                                    0.323        0.000                      0                 2277        0.036        0.000                      0                 2277        0.486        0.000                       0                  1052  
    rxoutclk_2                                                                                    0.545        0.000                      0                 2277        0.035        0.000                      0                 2277        0.486        0.000                       0                  1052  
    rxoutclk_3                                                                                    0.562        0.000                      0                 2277        0.033        0.000                      0                 2277        0.479        0.000                       0                  1052  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                                                  To Clock                                                                                        WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                  --------                                                                                        -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
mmcm_clkout6                                                                                mmcm_clkout0                                                                                      1.731        0.000                      0                  127                                                                        
gclkx                                                                                       mmcm_clkout0                                                                                      3.189        0.000                      0                   75        0.041        0.000                      0                   75  
lclks                                                                                       mmcm_clkout0                                                                                      0.221        0.000                      0                   29        0.072        0.000                      0                    1  
mmcm_clkout0                                                                                pll_clk[0]_DIV                                                                                    0.583        0.000                      0                  352        0.509        0.000                      0                  352  
mmcm_clkout0                                                                                pll_clk[1]_DIV                                                                                    1.372        0.000                      0                  352        0.463        0.000                      0                  352  
mmcm_clkout0                                                                                pll_clk[2]_DIV                                                                                    1.006        0.000                      0                  212        0.486        0.000                      0                  212  
mmcm_clkout0                                                                                mmcm_clkout6                                                                                      2.552        0.000                      0                   36        0.053        0.000                      0                    1  
lclks                                                                                       dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK        9.266        0.000                      0                    8                                                                        
drck2                                                                                       genblk1[0].user_clk_1                                                                             0.985        0.000                      0                   14        0.943        0.000                      0                   14  
gclkx                                                                                       genblk1[0].user_clk_1                                                                             0.285        0.000                      0                   46        1.553        0.000                      0                   24  
GTHE3_CHANNEL_RXOUTCLK[0]                                                                   genblk1[0].user_clk_1                                                                             2.899        0.000                      0                   17        0.037        0.000                      0                   17  
genblk1[0].user_clk_1                                                                       pipe_clk_1                                                                                        0.887        0.000                      0                  503        0.112        0.000                      0                  503  
gclkx                                                                                       gclkf                                                                                             3.812        0.000                      0                  123        0.037        0.000                      0                  123  
gclky                                                                                       gclkf                                                                                             0.561        0.000                      0                   34        0.037        0.000                      0                   34  
mmcm_clkout0                                                                                gclkx                                                                                             3.192        0.000                      0                   63        0.039        0.000                      0                   63  
genblk1[0].user_clk_1                                                                       gclkx                                                                                             2.568        0.000                      0                   14        0.035        0.000                      0                   14  
gclkf                                                                                       gclkx                                                                                             1.571        0.000                      0                  419        0.266        0.000                      0                  195  
gclky                                                                                       gclkx                                                                                             2.583        0.000                      0                  258        0.030        0.000                      0                  258  
GTHE3_CHANNEL_RXOUTCLK[0]                                                                   gclkx                                                                                             4.225        0.000                      0                   32        0.057        0.000                      0                   32  
GTHE3_CHANNEL_TXOUTCLK[0]                                                                   gclkx                                                                                             4.525        0.000                      0                   10        0.041        0.000                      0                   10  
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       gclkx                                                                                             4.693        0.000                      0                   29        0.053        0.000                      0                   29  
gclkx                                                                                       gclky                                                                                             0.558        0.000                      0                   39        0.066        0.000                      0                   37  
gclks                                                                                       gclky                                                                                             0.142        0.000                      0                   32        0.640        0.000                      0                   32  
GTHE3_CHANNEL_RXOUTCLK[0]                                                                   gclky                                                                                             4.147        0.000                      0                    8        0.039        0.000                      0                    8  
gclkx                                                                                       gclks                                                                                             1.800        0.000                      0                  226        0.039        0.000                      0                  146  
gclky                                                                                       gclks                                                                                             2.531        0.000                      0                   58        0.036        0.000                      0                   58  
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       gclks                                                                                             3.233        0.000                      0                   68        0.035        0.000                      0                   68  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  lclks                                                                                            32.128        0.000                      0                    8                                                                        
gclks                                                                                       lclks                                                                                             7.015        0.000                      0                    1        0.274        0.000                      0                    1  
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       rclkp                                                                                             1.743        0.000                      0                   12        0.047        0.000                      0                   12  
rxoutclk                                                                                    rclkp                                                                                             1.922        0.000                      0                    4        0.045        0.000                      0                    4  
rxoutclk_1                                                                                  rclkp                                                                                             1.834        0.000                      0                    4        0.093        0.000                      0                    4  
rxoutclk_2                                                                                  rclkp                                                                                             1.782        0.000                      0                    4        0.105        0.000                      0                    4  
rxoutclk_3                                                                                  rclkp                                                                                             1.855        0.000                      0                    4        0.050        0.000                      0                    4  
gclkx                                                                                       GTHE3_CHANNEL_RXOUTCLK[0]                                                                         1.507        0.000                      0                   64        1.412        0.000                      0                   33  
gclkx                                                                                       GTHE3_CHANNEL_TXOUTCLK[0]                                                                         1.455        0.000                      0                   71        1.356        0.000                      0                   40  
GTHE3_CHANNEL_RXOUTCLK[0]                                                                   GTHE3_CHANNEL_TXOUTCLK[0]                                                                         2.495        0.000                      0                   13        0.054        0.000                      0                   13  
gclkx                                                                                       gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                             0.165        0.000                      0                   67        1.377        0.000                      0                   58  
gclks                                                                                       gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                             0.390        0.000                      0                  532        1.327        0.000                      0                  460  
rxoutclk                                                                                    gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                             1.121        0.000                      0                   11        0.048        0.000                      0                   11  
rxoutclk_1                                                                                  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                             1.245        0.000                      0                   11        0.076        0.000                      0                   11  
rxoutclk_2                                                                                  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                             1.314        0.000                      0                   11        0.065        0.000                      0                   11  
rxoutclk_3                                                                                  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                             1.254        0.000                      0                   11        0.077        0.000                      0                   11  
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       rxoutclk                                                                                          0.582        0.000                      0                   16        0.084        0.000                      0                   16  
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       rxoutclk_1                                                                                        0.664        0.000                      0                   16        0.288        0.000                      0                   16  
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       rxoutclk_2                                                                                        0.641        0.000                      0                   16        0.199        0.000                      0                   16  
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       rxoutclk_3                                                                                        0.568        0.000                      0                   16        0.231        0.000                      0                   16  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                  From Clock                                                                                  To Clock                                                                                        WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                  ----------                                                                                  --------                                                                                        -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**                                                                           GTHE3_CHANNEL_RXOUTCLK[0]                                                                   GTHE3_CHANNEL_RXOUTCLK[0]                                                                         3.381        0.000                      0                    5        0.289        0.000                      0                    5  
**async_default**                                                                           gclkx                                                                                       GTHE3_CHANNEL_RXOUTCLK[0]                                                                                                                                               1.493        0.000                      0                   31  
**async_default**                                                                           GTHE3_CHANNEL_TXOUTCLK[0]                                                                   GTHE3_CHANNEL_TXOUTCLK[0]                                                                         3.537        0.000                      0                    5        0.202        0.000                      0                    5  
**async_default**                                                                           gclkx                                                                                       GTHE3_CHANNEL_TXOUTCLK[0]                                                                                                                                               1.948        0.000                      0                   31  
**async_default**                                                                           dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK       30.901        0.000                      0                  100        0.163        0.000                      0                  100  
**async_default**                                                                           gclkf                                                                                       gclkf                                                                                             1.665        0.000                      0                 1218        0.186        0.000                      0                 1218  
**async_default**                                                                           gclks                                                                                       gclks                                                                                             7.686        0.000                      0                  190        0.140        0.000                      0                  190  
**async_default**                                                                           gclkx                                                                                       gclks                                                                                                                                                                   0.473        0.000                      0                   80  
**async_default**                                                                           gclkf                                                                                       gclkx                                                                                                                                                                   0.392        0.000                      0                  224  
**async_default**                                                                           gclkx                                                                                       gclkx                                                                                             1.026        0.000                      0                  129        0.133        0.000                      0                  129  
**async_default**                                                                           gclkx                                                                                       gclky                                                                                                                                                                   0.721        0.000                      0                    2  
**async_default**                                                                           gclkx                                                                                       genblk1[0].user_clk_1                                                                                                                                                   1.653        0.000                      0                   22  
**async_default**                                                                           genblk1[0].user_clk_1                                                                       genblk1[0].user_clk_1                                                                             0.896        0.000                      0                    6        0.250        0.000                      0                    6  
**async_default**                                                                           gclks                                                                                       gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                                                                                                   1.433        0.000                      0                   72  
**async_default**                                                                           gclkx                                                                                       gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                                                                                                   1.736        0.000                      0                    9  
**async_default**                                                                           gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                             0.250        0.000                      0                  212        0.264        0.000                      0                  212  
**async_default**                                                                           rclkp                                                                                       gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                             1.663        0.000                      0                   20        0.067        0.000                      0                   20  
**async_default**                                                                           lclks                                                                                       lclks                                                                                             7.213        0.000                      0                  105        0.605        0.000                      0                  105  
**async_default**                                                                           gclks                                                                                       pclkp                                                                                             5.416        0.000                      0                    8        1.520        0.000                      0                    8  
**async_default**                                                                           pclkp                                                                                       pclkp                                                                                             8.894        0.000                      0                   27        0.255        0.000                      0                   27  
**async_default**                                                                           rclkp                                                                                       rclkp                                                                                             4.864        0.000                      0                   80        0.137        0.000                      0                   80  
**async_default**                                                                           gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       rxoutclk                                                                                          1.085        0.000                      0                    9        0.205        0.000                      0                    9  
**async_default**                                                                           rclkp                                                                                       rxoutclk                                                                                          1.818        0.000                      0                   20        0.086        0.000                      0                   20  
**async_default**                                                                           gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       rxoutclk_1                                                                                        0.625        0.000                      0                    9        0.714        0.000                      0                    9  
**async_default**                                                                           rclkp                                                                                       rxoutclk_1                                                                                        1.662        0.000                      0                   20        0.286        0.000                      0                   20  
**async_default**                                                                           gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       rxoutclk_2                                                                                        0.646        0.000                      0                    9        0.782        0.000                      0                    9  
**async_default**                                                                           rclkp                                                                                       rxoutclk_2                                                                                        1.937        0.000                      0                   20        0.055        0.000                      0                   20  
**async_default**                                                                           gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2                       rxoutclk_3                                                                                        0.657        0.000                      0                    9        0.753        0.000                      0                    9  
**async_default**                                                                           rclkp                                                                                       rxoutclk_3                                                                                        1.973        0.000                      0                   20        0.047        0.000                      0                   20  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  cclkp
  To Clock:  cclkp

Setup :            0  Failing Endpoints,  Worst Slack        1.727ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.056ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.727ns  (required time - arrival time)
  Source:                 mb/mig/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by cclkp  {rise@0.000ns fall@1.666ns period=3.333ns})
  Destination:            mb/mig/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
                            (rising edge-triggered cell FDRE clocked by cclkp  {rise@0.000ns fall@1.666ns period=3.333ns})
  Path Group:             cclkp
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.333ns  (cclkp rise@3.333ns - cclkp rise@0.000ns)
  Data Path Delay:        1.565ns  (logic 0.491ns (31.374%)  route 1.074ns (68.626%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        -0.066ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.172ns = ( 6.505 - 3.333 ) 
    Source Clock Delay      (SCD):    3.734ns
    Clock Pessimism Removal (CPR):    0.497ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.301ns (routing 1.026ns, distribution 1.275ns)
  Clock Net Delay (Destination): 2.044ns (routing 0.941ns, distribution 1.103ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock cclkp rise edge)      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X0Y2 (CLOCK_ROOT)    net (fo=18, routed)          2.301     3.734                         mb/mig/inst/u_ddr4_infrastructure/lopt
    SLICE_X3Y172         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X3Y172         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.117     3.851 f  AG_mb                mb/mig/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/Q
                         net (fo=7, routed)           0.472     4.323                         mb/mig/inst/u_ddr4_infrastructure/counter_input_rst[6]
    SLICE_X3Y172         LUT3 (Prop_B5LUT_SLICEL_I2_O)
                                                      0.160     4.483 f  AG_mb                mb/mig/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2/O
                         net (fo=1, routed)           0.203     4.686                         mb/mig/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2_n_0
    SLICE_X3Y171         LUT5 (Prop_B5LUT_SLICEL_I3_O)
                                                      0.214     4.900 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1/O
                         net (fo=1, routed)           0.399     5.299                         mb/mig/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1_n_0
    SLICE_X3Y171         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock cclkp rise edge)      3.333     3.333 r                       
    D23                                               0.000     3.333 r                       cclkp (IN)
                         net (fo=0)                   0.001     3.334                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     3.686 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     3.737                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     3.737 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     4.386                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     4.461 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X0Y2 (CLOCK_ROOT)    net (fo=18, routed)          2.044     6.505                         mb/mig/inst/u_ddr4_infrastructure/lopt
    SLICE_X3Y171         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/C
                         clock pessimism              0.497     7.001                           
                         clock uncertainty           -0.035     6.966                           
    SLICE_X3Y171         FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.060     7.026    AG_mb                  mb/mig/inst/u_ddr4_infrastructure/input_rst_mmcm_reg
  -------------------------------------------------------------------
                         required time                          7.026                           
                         arrival time                          -5.299                           
  -------------------------------------------------------------------
                         slack                                  1.727                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.056ns  (arrival time - required time)
  Source:                 mb/mig/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by cclkp  {rise@0.000ns fall@1.666ns period=3.333ns})
  Destination:            mb/mig/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
                            (rising edge-triggered cell FDSE clocked by cclkp  {rise@0.000ns fall@1.666ns period=3.333ns})
  Path Group:             cclkp
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (cclkp rise@0.000ns - cclkp rise@0.000ns)
  Data Path Delay:        0.117ns  (logic 0.064ns (54.701%)  route 0.053ns (45.299%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.005ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.062ns
    Source Clock Delay      (SCD):    1.624ns
    Clock Pessimism Removal (CPR):    0.433ns
  Clock Net Delay (Source):      1.005ns (routing 0.481ns, distribution 0.524ns)
  Clock Net Delay (Destination): 1.177ns (routing 0.534ns, distribution 0.643ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock cclkp rise edge)      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.213     0.214 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.028     0.242                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.242 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.350     0.592                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     0.619 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X0Y2 (CLOCK_ROOT)    net (fo=18, routed)          1.005     1.624                         mb/mig/inst/u_ddr4_infrastructure/lopt
    SLICE_X3Y172         FDSE                                         r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X3Y172         FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.049     1.673 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.037     1.710                         mb/mig/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X3Y172         LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.015     1.725 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1/O
                         net (fo=1, routed)           0.016     1.741                         mb/mig/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1_n_0
    SLICE_X3Y172         FDSE                                         r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock cclkp rise edge)      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.396     0.397 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.048     0.445                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.445 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.409     0.854                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     0.885 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X0Y2 (CLOCK_ROOT)    net (fo=18, routed)          1.177     2.062                         mb/mig/inst/u_ddr4_infrastructure/lopt
    SLICE_X3Y172         FDSE                                         r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism             -0.433     1.629                           
    SLICE_X3Y172         FDSE (Hold_CFF_SLICEL_C_D)
                                                      0.056     1.685    AG_mb                  mb/mig/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.685                           
                         arrival time                           1.741                           
  -------------------------------------------------------------------
                         slack                                  0.056                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         cclkp
Waveform(ns):       { 0.000 1.666 }
Period(ns):         3.333
Sources:            { cclkp }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFGCE/I           n/a            1.379         3.333       1.954      BUFGCE_X0Y103    mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/I
Low Pulse Width   Slow    MMCME3_ADV/CLKIN1  n/a            1.167         1.666       0.500      MMCME3_ADV_X0Y2  mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Slow    MMCME3_ADV/CLKIN1  n/a            1.167         1.666       0.500      MMCME3_ADV_X0Y2  mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        0.309ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.600ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.309ns  (required time - arrival time)
  Source:                 mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/lrdimm_drive_dq_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQ_reg[48]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (mmcm_clkout0 rise@4.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        3.517ns  (logic 0.208ns (5.914%)  route 3.309ns (94.086%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.171ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.685ns = ( 9.684 - 4.000 ) 
    Source Clock Delay      (SCD):    5.975ns
    Clock Pessimism Removal (CPR):    0.119ns
  Clock Uncertainty:      0.065ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.108ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.943ns (routing 0.335ns, distribution 1.608ns)
  Clock Net Delay (Destination): 1.679ns (routing 0.309ns, distribution 1.370ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     3.512 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.943     5.975                         mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][20]
    SLICE_X12Y140        FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/lrdimm_drive_dq_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X12Y140        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     6.089 r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/lrdimm_drive_dq_reg/Q
                         net (fo=513, routed)         3.273     9.362                         mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/lrdimm_drive_dq_reg_n_0
    SLICE_X7Y150         LUT4 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.094     9.456 r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQ[48]_i_1/O
                         net (fo=1, routed)           0.036     9.492                         mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQ[48]_i_1_n_0
    SLICE_X7Y150         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQ_reg[48]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock mmcm_clkout0 rise edge)
                                                      4.000     4.000 r                       
    D23                                               0.000     4.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     4.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     4.352 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     4.403                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     4.403 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     5.052                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     5.127 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096     7.223                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     7.558 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.372     7.930                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     8.005 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.679     9.684                         mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][20]
    SLICE_X7Y150         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQ_reg[48]/C
                         clock pessimism              0.119     9.804                           
                         clock uncertainty           -0.065     9.739                           
    SLICE_X7Y150         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.062     9.801    AG_mb                  mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQ_reg[48]
  -------------------------------------------------------------------
                         required time                          9.801                           
                         arrival time                          -9.492                           
  -------------------------------------------------------------------
                         slack                                  0.309                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 mb/mig/inst/u_ddr_cal_top/rdData_reg[272]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_reg[258]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.421ns  (logic 0.106ns (25.178%)  route 0.315ns (74.822%))
  Logic Levels:           0  
  Clock Path Skew:        0.284ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.048ns
    Source Clock Delay      (SCD):    5.712ns
    Clock Pessimism Removal (CPR):    0.052ns
  Clock Net Delay (Source):      1.706ns (routing 0.309ns, distribution 1.397ns)
  Clock Net Delay (Destination): 2.016ns (routing 0.335ns, distribution 1.681ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     0.353 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     0.404                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.404 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     1.053                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     1.128 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096     3.224                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     3.559 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.372     3.931                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     4.006 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.706     5.712                         mb/mig/inst/u_ddr_cal_top/dReg_reg[6]
    SLICE_X23Y112        FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/rdData_reg[272]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X23Y112        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.106     5.818 r  AG_mb                mb/mig/inst/u_ddr_cal_top/rdData_reg[272]/Q
                         net (fo=2, routed)           0.315     6.133                         mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/rdData[272]
    SLICE_X25Y120        FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_reg[258]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     3.512 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        2.016     6.048                         mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][20]
    SLICE_X25Y120        FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_reg[258]/C
                         clock pessimism             -0.052     5.996                           
    SLICE_X25Y120        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.107     6.103    AG_mb                  mb/mig/inst/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_reg[258]
  -------------------------------------------------------------------
                         required time                         -6.103                           
                         arrival time                           6.133                           
  -------------------------------------------------------------------
                         slack                                  0.030                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout0
Waveform(ns):       { 0.000 2.000 }
Period(ns):         4.000
Sources:            { mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.709         4.000       2.291      RAMB36_X3Y30    mb/cnt/qram/r32k.ram/CLKARDCLK
Low Pulse Width   Slow    PLLE3_ADV/CLKIN     n/a            1.400         2.000       0.600      PLLE3_ADV_X0Y3  mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE3_ADV/CLKIN     n/a            1.400         2.000       0.600      PLLE3_ADV_X0Y3  mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER/CLKIN



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]
  To Clock:  pll_clk[0]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.072ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]
Waveform(ns):       { 0.000 0.250 }
Period(ns):         0.500
Sources:            { mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.395         0.500       0.105      BITSLICE_CONTROL_X0Y8   mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.178         0.250       0.072      BITSLICE_CONTROL_X0Y8   mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.178         0.250       0.072      BITSLICE_CONTROL_X0Y8   mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.200        -1.222      1.022      BITSLICE_CONTROL_X0Y11  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]_DIV
  To Clock:  pll_clk[0]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.578ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]_DIV
Waveform(ns):       { 0.000 2.000 }
Period(ns):         4.000
Sources:            { mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] ... }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location              Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            3.160         4.000       0.840      BITSLICE_RX_TX_X0Y52  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.422         2.000       0.578      BITSLICE_RX_TX_X0Y52  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.422         2.000       0.578      BITSLICE_RX_TX_X0Y52  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]
  To Clock:  pll_clk[1]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.072ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]
Waveform(ns):       { 0.000 0.250 }
Period(ns):         0.500
Sources:            { mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.395         0.500       0.105      BITSLICE_CONTROL_X0Y16  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.178         0.250       0.072      BITSLICE_CONTROL_X0Y16  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.178         0.250       0.072      BITSLICE_CONTROL_X0Y16  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.200        -1.219      1.019      BITSLICE_CONTROL_X0Y19  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]_DIV
  To Clock:  pll_clk[1]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.578ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]_DIV
Waveform(ns):       { 0.000 2.000 }
Period(ns):         4.000
Sources:            { mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] ... }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            3.160         4.000       0.840      BITSLICE_RX_TX_X0Y104  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.422         2.000       0.578      BITSLICE_RX_TX_X0Y104  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.422         2.000       0.578      BITSLICE_RX_TX_X0Y104  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[2]
  To Clock:  pll_clk[2]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.072ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[2]
Waveform(ns):       { 0.000 0.250 }
Period(ns):         0.500
Sources:            { mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.395         0.500       0.105      BITSLICE_CONTROL_X0Y28  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.178         0.250       0.072      BITSLICE_CONTROL_X0Y28  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.178         0.250       0.072      BITSLICE_CONTROL_X0Y28  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[2]_DIV
  To Clock:  pll_clk[2]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.578ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[2]_DIV
Waveform(ns):       { 0.000 2.000 }
Period(ns):         4.000
Sources:            { mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26] mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT6[26] }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            3.160         4.000       0.840      BITSLICE_RX_TX_X0Y182  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.422         2.000       0.578      BITSLICE_RX_TX_X0Y182  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.422         2.000       0.578      BITSLICE_RX_TX_X0Y182  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        1.791ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.040ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.804ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.791ns  (required time - arrival time)
  Source:                 mb/mig/inst/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.lmb_as_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@4.000ns period=7.999ns})
  Destination:            mb/mig/inst/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@4.000ns period=7.999ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            7.999ns  (mmcm_clkout6 rise@7.999ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        5.503ns  (logic 0.741ns (13.465%)  route 4.762ns (86.535%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.691ns = ( 13.690 - 7.999 ) 
    Source Clock Delay      (SCD):    5.982ns
    Clock Pessimism Removal (CPR):    0.119ns
  Clock Uncertainty:      0.071ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.950ns (routing 0.335ns, distribution 1.615ns)
  Clock Net Delay (Destination): 1.685ns (routing 0.309ns, distribution 1.376ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT6)
                                                     -0.231     3.512 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y57         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=1742, routed)        1.950     5.982                         mb/mig/inst/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/LMB_Clk
    SLICE_X16Y164        FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.lmb_as_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X16Y164        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.116     6.098 r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/No_ECC.lmb_as_reg/Q
                         net (fo=1, routed)           0.238     6.336                         mb/mig/inst/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/lmb_as
    SLICE_X16Y164        LUT2 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.173     6.509 r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          1.102     7.611                         mb/mig/inst/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[0]
    SLICE_X21Y158        LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.205     7.816 r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          1.187     9.003                         mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[1].Gen_Sel_DFF/IReady
    SLICE_X19Y172        LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.115     9.118 r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[1].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.323     9.441                         mb/mig/inst/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/enb
    SLICE_X19Y164        LUT2 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.132     9.573 r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          1.912    11.485                         mb/mig/inst/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X1Y28         RAMB36E2                                     r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    ----------------------------------------

                         (clock mmcm_clkout6 rise edge)
                                                      7.999     7.999 r                       
    D23                                               0.000     7.999 r                       cclkp (IN)
                         net (fo=0)                   0.001     8.000                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     8.352 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     8.403                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     8.403 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     9.052                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     9.127 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096    11.223                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT6)
                                                      0.335    11.558 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.372    11.930                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y57         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075    12.005 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=1742, routed)        1.685    13.690                         mb/mig/inst/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/clkb
    RAMB36_X1Y28         RAMB36E2                                     r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism              0.119    13.809                           
                         clock uncertainty           -0.071    13.738                           
    RAMB36_X1Y28         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.462    13.276    AG_mb                  mb/mig/inst/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         13.276                           
                         arrival time                         -11.485                           
  -------------------------------------------------------------------
                         slack                                  1.791                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/wb_gpr_write_addr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@4.000ns period=7.999ns})
  Destination:            mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i/Using_FPGA.Native/RAMA/WADR2
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout6  {rise@0.000ns fall@4.000ns period=7.999ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.193ns  (logic 0.048ns (24.870%)  route 0.145ns (75.130%))
  Logic Levels:           0  
  Clock Path Skew:        0.078ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.028ns
    Source Clock Delay      (SCD):    2.893ns
    Clock Pessimism Removal (CPR):    0.057ns
  Clock Net Delay (Source):      0.813ns (routing 0.127ns, distribution 0.686ns)
  Clock Net Delay (Destination): 0.964ns (routing 0.142ns, distribution 0.822ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.213     0.214 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.028     0.242                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.242 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.350     0.592                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     0.619 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.997     1.616                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT6)
                                                      0.270     1.886 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.167     2.053                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y57         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     2.080 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=1742, routed)        0.813     2.893                         mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X18Y174        FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/wb_gpr_write_addr_reg[2]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X18Y174        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.048     2.941 r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/wb_gpr_write_addr_reg[2]/Q
                         net (fo=131, routed)         0.145     3.086                         mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i/Using_FPGA.Native/ADDRD2
    SLICE_X13Y174        RAMD32                                       r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i/Using_FPGA.Native/RAMA/WADR2
  -------------------------------------------------------------------    ----------------------------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.396     0.397 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.048     0.445                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.445 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.409     0.854                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     0.885 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.146     2.031                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT6)
                                                     -0.207     1.824 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.209     2.033                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y57         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     2.064 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=1742, routed)        0.964     3.028                         mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i/Using_FPGA.Native/WCLK
    SLICE_X13Y174        RAMD32                                       r  AG_mb                mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i/Using_FPGA.Native/RAMA/CLK
                         clock pessimism             -0.057     2.971                           
    SLICE_X13Y174        RAMD32 (Hold_E5LUT_SLICEM_CLK_WADR2)
                                                      0.075     3.046    AG_mb                  mb/mig/inst/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i/Using_FPGA.Native/RAMA
  -------------------------------------------------------------------
                         required time                         -3.046                           
                         arrival time                           3.086                           
  -------------------------------------------------------------------
                         slack                                  0.040                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout6
Waveform(ns):       { 0.000 4.000 }
Period(ns):         7.999
Sources:            { mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT6 }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       5.000         7.999       2.999      BITSLICE_CONTROL_X0Y8   mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       2.250         4.000       1.750      BITSLICE_CONTROL_X0Y8   mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       2.250         4.000       1.750      BITSLICE_CONTROL_X0Y8   mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.732         0.928       0.804      BITSLICE_CONTROL_X0Y15  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK



---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK

Setup :            0  Failing Endpoints,  Worst Slack       29.707ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.032ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       15.832ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             29.707ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {rise@0.000ns fall@16.500ns period=33.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {rise@0.000ns fall@16.500ns period=33.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
  Data Path Delay:        3.242ns  (logic 0.969ns (29.889%)  route 2.273ns (70.111%))
  Logic Levels:           5  (CARRY8=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.075ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.896ns = ( 38.896 - 33.000 ) 
    Source Clock Delay      (SCD):    7.135ns
    Clock Pessimism Removal (CPR):    1.164ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.437ns (routing 1.033ns, distribution 1.404ns)
  Clock Net Delay (Destination): 2.161ns (routing 0.947ns, distribution 1.214ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           4.615     4.615    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y106        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.698 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X0Y2 (CLOCK_ROOT)    net (fo=478, routed)         2.437     7.135    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X30Y138        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y138        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.114     7.249 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/Q
                         net (fo=50, routed)          0.807     8.056    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[0]
    SLICE_X27Y138        LUT4 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.116     8.172 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid_inferred_i_19/O
                         net (fo=2, routed)           0.474     8.646    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid[13]
    SLICE_X27Y136        LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.173     8.819 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_10/O
                         net (fo=1, routed)           0.000     8.819    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_10_n_0
    SLICE_X27Y136        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7])
                                                      0.352     9.171 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3/CO[7]
                         net (fo=4, routed)           0.700     9.871    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3_n_0
    SLICE_X31Y135        LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.040     9.911 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2/O
                         net (fo=7, routed)           0.270    10.181    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2_n_0
    SLICE_X31Y136        LUT3 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.174    10.355 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[3]_i_1/O
                         net (fo=1, routed)           0.022    10.377    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[3]_i_1_n_0
    SLICE_X31Y136        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
                                                     33.000    33.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.660    36.660    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y106        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075    36.735 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X0Y2 (CLOCK_ROOT)    net (fo=478, routed)         2.161    38.896    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X31Y136        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[3]/C
                         clock pessimism              1.164    40.060    
                         clock uncertainty           -0.035    40.025    
    SLICE_X31Y136        FDRE (Setup_FFF_SLICEL_C_D)
                                                      0.059    40.084    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[3]
  -------------------------------------------------------------------
                         required time                         40.084    
                         arrival time                         -10.377    
  -------------------------------------------------------------------
                         slack                                 29.707    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[15]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {rise@0.000ns fall@16.500ns period=33.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/I
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {rise@0.000ns fall@16.500ns period=33.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
  Data Path Delay:        0.135ns  (logic 0.048ns (35.556%)  route 0.087ns (64.444%))
  Logic Levels:           0  
  Clock Path Skew:        0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.443ns
    Source Clock Delay      (SCD):    3.432ns
    Clock Pessimism Removal (CPR):    0.970ns
  Clock Net Delay (Source):      1.067ns (routing 0.485ns, distribution 0.582ns)
  Clock Net Delay (Destination): 1.243ns (routing 0.538ns, distribution 0.705ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.338     2.338    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y106        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     2.365 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X0Y2 (CLOCK_ROOT)    net (fo=478, routed)         1.067     3.432    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/m_bscan_tck[0]
    SLICE_X30Y155        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y155        FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.048     3.480 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[15]/Q
                         net (fo=3, routed)           0.087     3.567    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/D
    SLICE_X30Y156        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/I
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.169     3.169    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y106        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     3.200 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X0Y2 (CLOCK_ROOT)    net (fo=478, routed)         1.243     4.443    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/WCLK
    SLICE_X30Y156        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/CLK
                         clock pessimism             -0.970     3.473    
    SLICE_X30Y156        RAMD32 (Hold_G6LUT_SLICEM_CLK_I)
                                                      0.062     3.535    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP
  -------------------------------------------------------------------
                         required time                         -3.535    
                         arrival time                           3.567    
  -------------------------------------------------------------------
                         slack                                  0.032    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
Waveform(ns):       { 0.000 16.500 }
Period(ns):         33.000
Sources:            { dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I    n/a            1.379         33.000      31.621     BUFGCE_X0Y106  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/I
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.668         16.500      15.832     SLICE_X29Y156  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.668         16.500      15.832     SLICE_X29Y156  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  drck1
  To Clock:  drck1

Setup :            0  Failing Endpoints,  Worst Slack       19.609ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.119ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        9.725ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             19.609ns  (required time - arrival time)
  Source:                 bsif/sel1d_reg/C
                            (falling edge-triggered cell FDCE clocked by drck1  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bsif/fcs_reg/D
                            (falling edge-triggered cell FDCE clocked by drck1  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             drck1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (drck1 fall@30.000ns - drck1 fall@10.000ns)
  Data Path Delay:        0.415ns  (logic 0.116ns (27.952%)  route 0.299ns (72.048%))
  Logic Levels:           0  
  Clock Path Skew:        -0.001ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.478ns = ( 30.478 - 30.000 ) 
    Source Clock Delay      (SCD):    0.597ns = ( 10.597 - 10.000 ) 
    Clock Pessimism Removal (CPR):    0.118ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock drck1 fall edge)     10.000    10.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    10.000 f  bsif/bs1/DRCK
                         net (fo=3, routed)           0.597    10.597    bsif/bs1_0
    SLICE_X88Y102        FDCE                                         r  bsif/sel1d_reg/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y102        FDCE (Prop_EFF2_SLICEL_C_Q)
                                                      0.116    10.713 r  bsif/sel1d_reg/Q
                         net (fo=1, routed)           0.299    11.012    bsif/sel1d
    SLICE_X88Y102        FDCE                                         r  bsif/fcs_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock drck1 fall edge)     30.000    30.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    30.000 f  bsif/bs1/DRCK
                         net (fo=3, routed)           0.478    30.478    bsif/bs1_0
    SLICE_X88Y102        FDCE                                         r  bsif/fcs_reg/C  (IS_INVERTED)
                         clock pessimism              0.118    30.596    
                         clock uncertainty           -0.035    30.561    
    SLICE_X88Y102        FDCE (Setup_EFF_SLICEL_C_D)
                                                      0.060    30.621    bsif/fcs_reg
  -------------------------------------------------------------------
                         required time                         30.621    
                         arrival time                         -11.012    
  -------------------------------------------------------------------
                         slack                                 19.609    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 bsif/sel1d_reg/C
                            (falling edge-triggered cell FDCE clocked by drck1  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bsif/fcs_reg/D
                            (falling edge-triggered cell FDCE clocked by drck1  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             drck1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (drck1 fall@10.000ns - drck1 fall@10.000ns)
  Data Path Delay:        0.179ns  (logic 0.048ns (26.816%)  route 0.131ns (73.184%))
  Logic Levels:           0  
  Clock Path Skew:        0.004ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.380ns = ( 10.380 - 10.000 ) 
    Source Clock Delay      (SCD):    0.285ns = ( 10.285 - 10.000 ) 
    Clock Pessimism Removal (CPR):    0.091ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock drck1 fall edge)     10.000    10.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    10.000 f  bsif/bs1/DRCK
                         net (fo=3, routed)           0.285    10.285    bsif/bs1_0
    SLICE_X88Y102        FDCE                                         r  bsif/sel1d_reg/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y102        FDCE (Prop_EFF2_SLICEL_C_Q)
                                                      0.048    10.333 r  bsif/sel1d_reg/Q
                         net (fo=1, routed)           0.131    10.464    bsif/sel1d
    SLICE_X88Y102        FDCE                                         r  bsif/fcs_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock drck1 fall edge)     10.000    10.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    10.000 f  bsif/bs1/DRCK
                         net (fo=3, routed)           0.380    10.380    bsif/bs1_0
    SLICE_X88Y102        FDCE                                         r  bsif/fcs_reg/C  (IS_INVERTED)
                         clock pessimism             -0.091    10.289    
    SLICE_X88Y102        FDCE (Hold_EFF_SLICEL_C_D)
                                                      0.056    10.345    bsif/fcs_reg
  -------------------------------------------------------------------
                         required time                        -10.345    
                         arrival time                          10.464    
  -------------------------------------------------------------------
                         slack                                  0.119    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         drck1
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { bsif/bs1/DRCK }

Check Type        Corner  Lib Pin  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     FDCE/C   n/a            0.550         20.000      19.450     SLICE_X88Y102  bsif/fcs_reg/C
Low Pulse Width   Slow    FDCE/C   n/a            0.275         10.000      9.725      SLICE_X88Y102  bsif/fcs_reg/C
High Pulse Width  Slow    FDCE/C   n/a            0.275         10.000      9.725      SLICE_X88Y102  bsif/fcs_reg/C



---------------------------------------------------------------------------------------------------
From Clock:  drck2
  To Clock:  drck2

Setup :            0  Failing Endpoints,  Worst Slack       15.471ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.034ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        9.146ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             15.471ns  (required time - arrival time)
  Source:                 bsif/cpage_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by drck2  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            tport/tpts_reg_lopt_replica_6/CE
                            (rising edge-triggered cell FDRE clocked by drck2  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             drck2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (drck2 rise@20.000ns - drck2 rise@0.000ns)
  Data Path Delay:        4.031ns  (logic 0.454ns (11.263%)  route 3.577ns (88.737%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.415ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.574ns = ( 23.574 - 20.000 ) 
    Source Clock Delay      (SCD):    4.478ns
    Clock Pessimism Removal (CPR):    0.489ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.260ns (routing 0.335ns, distribution 1.925ns)
  Clock Net Delay (Destination): 1.806ns (routing 0.309ns, distribution 1.497ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock drck2 rise edge)      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  bsif/bs/DRCK
                         net (fo=1, routed)           2.135     2.135    bsif/drck2
    BUFGCE_X1Y52         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     2.218 r  bsif/_clk/O
    X2Y2 (CLOCK_ROOT)    net (fo=255, routed)         2.260     4.478    bsif/CLK
    SLICE_X94Y97         FDRE                                         r  bsif/cpage_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y97         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.116     4.594 f  bsif/cpage_reg[4]/Q
                         net (fo=23, routed)          0.380     4.974    bsif/D[11]
    SLICE_X94Y98         LUT4 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.135     5.109 f  bsif/cinc_i_3/O
                         net (fo=13, routed)          0.323     5.432    bsif/cinc_i_3_n_0
    SLICE_X93Y98         LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.071     5.503 r  bsif/tpts_i_4/O
                         net (fo=1, routed)           0.070     5.573    bsif/paget
    SLICE_X93Y98         LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.132     5.705 r  bsif/tpts_i_2/O
                         net (fo=8, routed)           2.804     8.509    tport/wtps
    SLICE_X49Y17         FDRE                                         r  tport/tpts_reg_lopt_replica_6/CE
  -------------------------------------------------------------------    -------------------

                         (clock drck2 rise edge)     20.000    20.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    20.000 r  bsif/bs/DRCK
                         net (fo=1, routed)           1.693    21.693    bsif/drck2
    BUFGCE_X1Y52         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075    21.768 r  bsif/_clk/O
    X2Y2 (CLOCK_ROOT)    net (fo=255, routed)         1.806    23.574    tport/CLK
    SLICE_X49Y17         FDRE                                         r  tport/tpts_reg_lopt_replica_6/C
                         clock pessimism              0.489    24.063    
                         clock uncertainty           -0.035    24.028    
    SLICE_X49Y17         FDRE (Setup_AFF2_SLICEL_C_CE)
                                                     -0.048    23.980    tport/tpts_reg_lopt_replica_6
  -------------------------------------------------------------------
                         required time                         23.980    
                         arrival time                          -8.509    
  -------------------------------------------------------------------
                         slack                                 15.471    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 ppc/cdataw_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by drck2  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            ppc/dsr/dpw[0].sdr.inst/r32k.ram/DINBDIN[2]
                            (rising edge-triggered cell RAMB36E2 clocked by drck2  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             drck2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (drck2 rise@0.000ns - drck2 rise@0.000ns)
  Data Path Delay:        0.147ns  (logic 0.048ns (32.653%)  route 0.099ns (67.347%))
  Logic Levels:           0  
  Clock Path Skew:        0.084ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.483ns
    Source Clock Delay      (SCD):    1.906ns
    Clock Pessimism Removal (CPR):    0.493ns
  Clock Net Delay (Source):      0.858ns (routing 0.127ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.063ns (routing 0.142ns, distribution 0.921ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock drck2 rise edge)      0.000     0.000 r                       
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r                       bsif/bs/DRCK
                         net (fo=1, routed)           1.021     1.021                         bsif/drck2
    BUFGCE_X1Y52         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.048 r                       bsif/_clk/O
    X2Y2 (CLOCK_ROOT)    net (fo=255, routed)         0.858     1.906                         ppc/CLK
    SLICE_X60Y139        FDRE                                         r  AG_dmac/AG_ppc       ppc/cdataw_reg[26]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X60Y139        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.048     1.954 r  AG_dmac/AG_ppc       ppc/cdataw_reg[26]/Q
                         net (fo=3, routed)           0.099     2.053                         ppc/dsr/dpw[0].sdr.inst/r32k.ram_2[2]
    RAMB36_X6Y28         RAMB36E2                                     r  AG_dmac/AG_ppc       ppc/dsr/dpw[0].sdr.inst/r32k.ram/DINBDIN[2]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock drck2 rise edge)      0.000     0.000 r                       
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r                       bsif/bs/DRCK
                         net (fo=1, routed)           1.389     1.389                         bsif/drck2
    BUFGCE_X1Y52         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.420 r                       bsif/_clk/O
    X2Y2 (CLOCK_ROOT)    net (fo=255, routed)         1.063     2.483                         ppc/dsr/dpw[0].sdr.inst/CLK
    RAMB36_X6Y28         RAMB36E2                                     r  AG_dmac/AG_ppc       ppc/dsr/dpw[0].sdr.inst/r32k.ram/CLKBWRCLK
                         clock pessimism             -0.493     1.990                           
    RAMB36_X6Y28         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[2])
                                                      0.029     2.019    AG_dmac/AG_ppc         ppc/dsr/dpw[0].sdr.inst/r32k.ram
  -------------------------------------------------------------------
                         required time                         -2.019                           
                         arrival time                           2.053                           
  -------------------------------------------------------------------
                         slack                                  0.034                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         drck2
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { bsif/bs/DRCK }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.709         20.000      18.291     RAMB36_X8Y38  niop/bnk/prc/dsr0/dpw[0].sdr.inst/r32k.ram/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.854         10.000      9.146      RAMB36_X8Y38  niop/bnk/prc/dsr0/dpw[0].sdr.inst/r32k.ram/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.854         10.000      9.146      RAMB36_X8Y38  niop/bnk/prc/dsr0/dpw[0].sdr.inst/r32k.ram/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  pclkp
  To Clock:  pclkp

Setup :            0  Failing Endpoints,  Worst Slack        8.472ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.041ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.442ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             8.472ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by pclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[5]/D
                            (rising edge-triggered cell FDCE clocked by pclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             pclkp
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (pclkp rise@10.000ns - pclkp rise@0.000ns)
  Data Path Delay:        1.430ns  (logic 0.423ns (29.580%)  route 1.007ns (70.420%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        -0.123ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.388ns = ( 12.388 - 10.000 ) 
    Source Clock Delay      (SCD):    2.848ns
    Clock Pessimism Removal (CPR):    0.337ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.070ns (routing 0.759ns, distribution 1.311ns)
  Clock Net Delay (Destination): 1.833ns (routing 0.687ns, distribution 1.146ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock pclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       pclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/pclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.381     0.381 r                       sc/mgtp/ODIV2
                         net (fo=2, routed)           0.082     0.463                         nvmp/genblk1[0].pcif_i/inst/sys_clk
    BUFG_GT_X0Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.778 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/O
    X3Y1 (CLOCK_ROOT)    net (fo=143, routed)         2.070     2.848                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/sys_clk_bufg
    SLICE_X97Y72         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[3]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X97Y72         FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.117     2.965 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[3]/Q
                         net (fo=4, routed)           0.424     3.389                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg_n_0_[3]
    SLICE_X98Y72         LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.173     3.562 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt[8]_i_2/O
                         net (fo=4, routed)           0.299     3.861                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt[8]_i_2_n_0
    SLICE_X98Y72         LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.133     3.994 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt[5]_i_1/O
                         net (fo=1, routed)           0.284     4.278                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt[5]
    SLICE_X98Y72         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[5]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pclkp rise edge)     10.000    10.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r                       pclkp (IN)
                         net (fo=0)                   0.000    10.000                         sc/pclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.226    10.226 r                       sc/mgtp/ODIV2
                         net (fo=2, routed)           0.046    10.272                         nvmp/genblk1[0].pcif_i/inst/sys_clk
    BUFG_GT_X0Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283    10.555 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/O
    X3Y1 (CLOCK_ROOT)    net (fo=143, routed)         1.833    12.388                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/sys_clk_bufg
    SLICE_X98Y72         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[5]/C
                         clock pessimism              0.337    12.726                           
                         clock uncertainty           -0.035    12.690                           
    SLICE_X98Y72         FDCE (Setup_EFF_SLICEL_C_D)
                                                      0.060    12.750    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[5]
  -------------------------------------------------------------------
                         required time                         12.750                           
                         arrival time                          -4.278                           
  -------------------------------------------------------------------
                         slack                                  8.472                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by pclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[4]/D
                            (rising edge-triggered cell FDCE clocked by pclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             pclkp
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclkp rise@0.000ns - pclkp rise@0.000ns)
  Data Path Delay:        0.189ns  (logic 0.094ns (49.735%)  route 0.095ns (50.265%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.560ns
    Source Clock Delay      (SCD):    1.239ns
    Clock Pessimism Removal (CPR):    0.229ns
  Clock Net Delay (Source):      0.938ns (routing 0.390ns, distribution 0.548ns)
  Clock Net Delay (Destination): 1.124ns (routing 0.441ns, distribution 0.683ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock pclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       pclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/pclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.183     0.183 r                       sc/mgtp/ODIV2
                         net (fo=2, routed)           0.018     0.201                         nvmp/genblk1[0].pcif_i/inst/sys_clk
    BUFG_GT_X0Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.301 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/O
    X3Y1 (CLOCK_ROOT)    net (fo=143, routed)         0.938     1.239                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/sys_clk_bufg
    SLICE_X96Y72         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[0]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y72         FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.049     1.288 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[0]/Q
                         net (fo=6, routed)           0.079     1.367                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg_n_0_[0]
    SLICE_X98Y72         LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.045     1.412 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt[4]_i_1/O
                         net (fo=1, routed)           0.016     1.428                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt[4]
    SLICE_X98Y72         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[4]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       pclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/pclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.271     0.271 r                       sc/mgtp/ODIV2
                         net (fo=2, routed)           0.035     0.306                         nvmp/genblk1[0].pcif_i/inst/sys_clk
    BUFG_GT_X0Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.436 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/O
    X3Y1 (CLOCK_ROOT)    net (fo=143, routed)         1.124     1.560                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/sys_clk_bufg
    SLICE_X98Y72         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[4]/C
                         clock pessimism             -0.229     1.331                           
    SLICE_X98Y72         FDCE (Hold_HFF_SLICEL_C_D)
                                                      0.056     1.387    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_cnt_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.387                           
                         arrival time                           1.428                           
  -------------------------------------------------------------------
                         slack                                  0.041                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pclkp
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { pclkp }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFG_GT/I   n/a            1.379         10.000      8.621      BUFG_GT_X0Y54  nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/I
Low Pulse Width   Slow    SRL16E/CLK  n/a            0.558         5.000       4.442      SLICE_X100Y69  nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_r_reg[2]_srl3/CLK
High Pulse Width  Slow    SRL16E/CLK  n/a            0.558         5.000       4.442      SLICE_X100Y69  nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/cpllreset_r_reg[2]_srl3/CLK



---------------------------------------------------------------------------------------------------
From Clock:  txoutclk_out[0]_1
  To Clock:  txoutclk_out[0]_1

Setup :            0  Failing Endpoints,  Worst Slack        0.194ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.031ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.194ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/CORECLKMICOMPLETIONRAML
                            (rising edge-triggered cell PCIE_3_1 clocked by txoutclk_out[0]_1  {rise@0.000ns fall@1.000ns period=2.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[3].ramb18e2_inst/ADDRBWRADDR[4]
                            (rising edge-triggered cell RAMB18E2 clocked by txoutclk_out[0]_1  {rise@0.000ns fall@1.000ns period=2.000ns})
  Path Group:             txoutclk_out[0]_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.000ns  (txoutclk_out[0]_1 rise@2.000ns - txoutclk_out[0]_1 rise@0.000ns)
  Data Path Delay:        1.022ns  (logic 0.327ns (31.996%)  route 0.695ns (68.004%))
  Logic Levels:           0  
  Clock Path Skew:        -0.106ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.957ns = ( 3.957 - 2.000 ) 
    Source Clock Delay      (SCD):    2.233ns
    Clock Pessimism Removal (CPR):    0.170ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.616ns, distribution 1.220ns)
  Clock Net Delay (Destination): 1.628ns (routing 0.557ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock txoutclk_out[0]_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.082     0.082                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y41        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_coreclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=33, routed)          1.836     2.233                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/CORECLKMIREQUESTRAM
    PCIE_3_1_X0Y0        PCIE_3_1                                     r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/CORECLKMICOMPLETIONRAML
  -------------------------------------------------------------------    ----------------------------------------
    PCIE_3_1_X0Y0        PCIE_3_1 (Prop_PCIE_3_1_CORECLKMICOMPLETIONRAML_MICOMPLETIONRAMREADADDRESSBL[0])
                                                      0.327     2.560 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/MICOMPLETIONRAMREADADDRESSBL[0]
                         net (fo=2, routed)           0.695     3.255                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[3].ramb18e2_inst_1[0]
    RAMB18_X9Y11         RAMB18E2                                     r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[3].ramb18e2_inst/ADDRBWRADDR[4]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock txoutclk_out[0]_1 rise edge)
                                                      2.000     2.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     2.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.046     2.046                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y41        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     2.329 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_coreclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=33, routed)          1.628     3.957                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/CORECLKMIREQUESTRAM
    RAMB18_X9Y11         RAMB18E2                                     r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[3].ramb18e2_inst/CLKBWRCLK
                         clock pessimism              0.170     4.127                           
                         clock uncertainty           -0.035     4.092                           
    RAMB18_X9Y11         RAMB18E2 (Setup_RAMB18E2_U_RAMB181_CLKBWRCLK_ADDRBWRADDR[4])
                                                     -0.643     3.449    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[3].ramb18e2_inst
  -------------------------------------------------------------------
                         required time                          3.449                           
                         arrival time                          -3.255                           
  -------------------------------------------------------------------
                         slack                                  0.194                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_req_inst/bram_req_8k_inst/RAMB18E2[3].ramb18e2_inst/CLKARDCLK
                            (rising edge-triggered cell RAMB18E2 clocked by txoutclk_out[0]_1  {rise@0.000ns fall@1.000ns period=2.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/MIREQUESTRAMREADDATA[137]
                            (rising edge-triggered cell PCIE_3_1 clocked by txoutclk_out[0]_1  {rise@0.000ns fall@1.000ns period=2.000ns})
  Path Group:             txoutclk_out[0]_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (txoutclk_out[0]_1 rise@0.000ns - txoutclk_out[0]_1 rise@0.000ns)
  Data Path Delay:        0.367ns  (logic 0.136ns (37.057%)  route 0.231ns (62.943%))
  Logic Levels:           0  
  Clock Path Skew:        0.032ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.131ns
    Source Clock Delay      (SCD):    0.964ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      0.846ns (routing 0.313ns, distribution 0.533ns)
  Clock Net Delay (Destination): 0.966ns (routing 0.357ns, distribution 0.609ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock txoutclk_out[0]_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.018     0.018                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y41        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_coreclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=33, routed)          0.846     0.964                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_req_inst/bram_req_8k_inst/CORECLKMIREQUESTRAM
    RAMB18_X8Y5          RAMB18E2                                     r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_req_inst/bram_req_8k_inst/RAMB18E2[3].ramb18e2_inst/CLKARDCLK
  -------------------------------------------------------------------    ----------------------------------------
    RAMB18_X8Y5          RAMB18E2 (Prop_RAMB18E2_U_RAMB181_CLKARDCLK_DOUTBDOUT[10])
                                                      0.136     1.100 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_req_inst/bram_req_8k_inst/RAMB18E2[3].ramb18e2_inst/DOUTBDOUT[10]
                         net (fo=1, routed)           0.231     1.331                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/MIREQUESTRAMREADDATA[137]
    PCIE_3_1_X0Y0        PCIE_3_1                                     r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/MIREQUESTRAMREADDATA[137]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock txoutclk_out[0]_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.035     0.035                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y41        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_coreclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=33, routed)          0.966     1.131                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/CORECLKMIREQUESTRAM
    PCIE_3_1_X0Y0        PCIE_3_1                                     r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/CORECLK
                         clock pessimism             -0.135     0.996                           
    PCIE_3_1_X0Y0        PCIE_3_1 (Hold_PCIE_3_1_CORECLK_MIREQUESTRAMREADDATA[137])
                                                      0.304     1.300    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst
  -------------------------------------------------------------------
                         required time                         -1.300                           
                         arrival time                           1.331                           
  -------------------------------------------------------------------
                         slack                                  0.031                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         txoutclk_out[0]_1
Waveform(ns):       { 0.000 1.000 }
Period(ns):         2.000
Sources:            { nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK }

Check Type        Corner  Lib Pin             Reference Pin     Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     PCIE_3_1/CORECLK    n/a               2.000         2.000       0.000      PCIE_3_1_X0Y0  nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/CORECLK
Low Pulse Width   Slow    RAMB18E2/CLKARDCLK  n/a               0.980         1.000       0.020      RAMB18_X8Y6    nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[0].ramb18e2_inst/CLKARDCLK
High Pulse Width  Slow    RAMB18E2/CLKARDCLK  n/a               0.980         1.000       0.020      RAMB18_X8Y6    nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[0].ramb18e2_inst/CLKARDCLK
Max Skew          Fast    PCIE_3_1/CORECLK    PCIE_3_1/USERCLK  0.374         0.206       0.168      PCIE_3_1_X0Y0  nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/CORECLK



---------------------------------------------------------------------------------------------------
From Clock:  genblk1[0].user_clk_1
  To Clock:  genblk1[0].user_clk_1

Setup :            0  Failing Endpoints,  Worst Slack        0.048ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.031ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.048ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_OUTPUT_INST/ALU_OUT[10]
                            (rising edge-triggered cell DSP_OUTPUT clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             genblk1[0].user_clk_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (genblk1[0].user_clk_1 rise@4.000ns - genblk1[0].user_clk_1 rise@0.000ns)
  Data Path Delay:        3.826ns  (logic 2.681ns (70.073%)  route 1.145ns (29.927%))
  Logic Levels:           6  (DSP_A_B_DATA=1 DSP_ALU=1 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_PREADD_DATA=1 LUT5=1)
  Clock Path Skew:        -0.006ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.006ns = ( 6.006 - 4.000 ) 
    Source Clock Delay      (SCD):    2.295ns
    Clock Pessimism Removal (CPR):    0.283ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.898ns (routing 0.606ns, distribution 1.292ns)
  Clock Net Delay (Destination): 1.677ns (routing 0.548ns, distribution 1.129ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.082     0.082                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.898     2.295                         nvmp/genblk1[0].prc/j1/jdsp/dsp/CLK
    DSP48E2_X15Y44       DSP_OUTPUT                                   r  AG_nvmprc            nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    ----------------------------------------
    DSP48E2_X15Y44       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[20])
                                                      0.306     2.601 f  AG_nvmprc            nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_OUTPUT_INST/P[20]
                         net (fo=6, routed)           0.791     3.392                         nvmp/genblk1[0].prc/j1/jdsp/stkp[20]
    SLICE_X83Y109        LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.205     3.597 f  AG_nvmprc            nvmp/genblk1[0].prc/j1/jdsp/dsp_i_23__0/O
                         net (fo=1, routed)           0.354     3.951                         nvmp/genblk1[0].prc/j1/jdsp/dsp/A[2]
    DSP48E2_X15Y44       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[2]_A2_DATA[2])
                                                      0.337     4.288 r  AG_nvmprc            nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_A_B_DATA_INST/A2_DATA[2]
                         net (fo=1, routed)           0.000     4.288                         nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_A_B_DATA.A2_DATA<2>
    DSP48E2_X15Y44       DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[2]_A2A1[2])
                                                      0.155     4.443 r  AG_nvmprc            nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_PREADD_DATA_INST/A2A1[2]
                         net (fo=1, routed)           0.000     4.443                         nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_PREADD_DATA.A2A1<2>
    DSP48E2_X15Y44       DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[2]_U[10])
                                                      0.866     5.309 f  AG_nvmprc            nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_MULTIPLIER_INST/U[10]
                         net (fo=1, routed)           0.000     5.309                         nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_MULTIPLIER.U<10>
    DSP48E2_X15Y44       DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[10]_U_DATA[10])
                                                      0.110     5.419 r  AG_nvmprc            nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_M_DATA_INST/U_DATA[10]
                         net (fo=1, routed)           0.000     5.419                         nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_M_DATA.U_DATA<10>
    DSP48E2_X15Y44       DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[10]_ALU_OUT[10])
                                                      0.702     6.121 r  AG_nvmprc            nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_ALU_INST/ALU_OUT[10]
                         net (fo=1, routed)           0.000     6.121                         nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_ALU.ALU_OUT<10>
    DSP48E2_X15Y44       DSP_OUTPUT                                   r  AG_nvmprc            nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_OUTPUT_INST/ALU_OUT[10]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock genblk1[0].user_clk_1 rise edge)
                                                      4.000     4.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     4.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.046     4.046                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.329 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.677     6.006                         nvmp/genblk1[0].prc/j1/jdsp/dsp/CLK
    DSP48E2_X15Y44       DSP_OUTPUT                                   r  AG_nvmprc            nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.283     6.289                           
                         clock uncertainty           -0.035     6.254                           
    DSP48E2_X15Y44       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[10])
                                                     -0.085     6.169    AG_nvmprc              nvmp/genblk1[0].prc/j1/jdsp/dsp/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          6.169                           
                         arrival time                          -6.121                           
  -------------------------------------------------------------------
                         slack                                  0.048                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].ctag_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/SAXISCCTDATA[71]
                            (rising edge-triggered cell PCIE_3_1 clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             genblk1[0].user_clk_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (genblk1[0].user_clk_1 rise@0.000ns - genblk1[0].user_clk_1 rise@0.000ns)
  Data Path Delay:        0.371ns  (logic 0.079ns (21.294%)  route 0.292ns (78.706%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.125ns
    Source Clock Delay      (SCD):    0.947ns
    Clock Pessimism Removal (CPR):    0.133ns
  Clock Net Delay (Source):      0.829ns (routing 0.306ns, distribution 0.523ns)
  Clock Net Delay (Destination): 0.960ns (routing 0.348ns, distribution 0.612ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.018     0.018                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         0.829     0.947                         nvmp/genblk1[0].user_clk
    SLICE_X86Y19         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].ctag_reg[7]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X86Y19         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.048     0.995 r  AG_nvmp              nvmp/genblk1[0].ctag_reg[7]/Q
                         net (fo=1, routed)           0.032     1.027                         nvmp/genblk1[0].nvmry/dpw[0].sdr.inst/PCIE_3_1_inst_5[7]
    SLICE_X86Y19         LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.031     1.058 r  AG_nvmp              nvmp/genblk1[0].nvmry/dpw[0].sdr.inst/PCIE_3_1_inst_i_64/O
                         net (fo=1, routed)           0.260     1.318                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/SAXISCCTDATA[71]
    PCIE_3_1_X0Y0        PCIE_3_1                                     r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/SAXISCCTDATA[71]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.035     0.035                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         0.960     1.125                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/CLK_USERCLK
    PCIE_3_1_X0Y0        PCIE_3_1                                     r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/USERCLK
                         clock pessimism             -0.133     0.992                           
    PCIE_3_1_X0Y0        PCIE_3_1 (Hold_PCIE_3_1_USERCLK_SAXISCCTDATA[71])
                                                      0.295     1.287    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst
  -------------------------------------------------------------------
                         required time                         -1.287                           
                         arrival time                           1.318                           
  -------------------------------------------------------------------
                         slack                                  0.031                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         genblk1[0].user_clk_1
Waveform(ns):       { 0.000 2.000 }
Period(ns):         4.000
Sources:            { nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O }

Check Type        Corner  Lib Pin             Reference Pin     Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     PCIE_3_1/USERCLK    n/a               4.000         4.000       0.000      PCIE_3_1_X0Y0  nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/USERCLK
Low Pulse Width   Slow    RAMB18E2/CLKARDCLK  n/a               0.854         2.000       1.146      RAMB18_X9Y40   nvmp/genblk1[0].cf0/ram/dpr/dpw[0].sdr.inst/r16k.ram/CLKARDCLK
High Pulse Width  Slow    RAMB18E2/CLKARDCLK  n/a               0.854         2.000       1.146      RAMB18_X9Y40   nvmp/genblk1[0].cf0/ram/dpr/dpw[0].sdr.inst/r16k.ram/CLKARDCLK
Max Skew          Fast    PCIE_3_1/USERCLK    PCIE_3_1/CORECLK  0.374         0.193       0.181      PCIE_3_1_X0Y0  nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/USERCLK



---------------------------------------------------------------------------------------------------
From Clock:  mcap_clk_1
  To Clock:  mcap_clk_1

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mcap_clk_1
Waveform(ns):       { 0.000 4.000 }
Period(ns):         8.000
Sources:            { nvmp/genblk1[0].pcif_i/inst/gt_top_i/bufg_mcap_clk/O }

Check Type  Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period  n/a     PCIE_3_1/MCAPCLK  n/a            8.000         8.000       0.000      PCIE_3_1_X0Y0  nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/MCAPCLK



---------------------------------------------------------------------------------------------------
From Clock:  pipe_clk_1
  To Clock:  pipe_clk_1

Setup :            0  Failing Endpoints,  Worst Slack        0.538ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.031ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.538ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/prst_n_r_reg_reg/C
                            (rising edge-triggered cell FDCE clocked by pipe_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_lane[1].phy_txeq_i/TXEQ_MAINCURSOR_reg[5]/CE
                            (rising edge-triggered cell FDRE clocked by pipe_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             pipe_clk_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (pipe_clk_1 rise@4.000ns - pipe_clk_1 rise@0.000ns)
  Data Path Delay:        3.165ns  (logic 0.186ns (5.877%)  route 2.979ns (94.123%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.212ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.982ns = ( 5.982 - 4.000 ) 
    Source Clock Delay      (SCD):    2.322ns
    Clock Pessimism Removal (CPR):    0.128ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.925ns (routing 0.623ns, distribution 1.302ns)
  Clock Net Delay (Destination): 1.653ns (routing 0.563ns, distribution 1.090ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock pipe_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.082     0.082                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y43        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_pclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=1126, routed)        1.925     2.322                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/CLK_PCLK
    SLICE_X91Y65         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/prst_n_r_reg_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y65         FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     2.436 f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/prst_n_r_reg_reg/Q
                         net (fo=209, routed)         1.657     4.093                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_lane[1].phy_txeq_i/D[0]
    SLICE_X88Y40         LUT4 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.072     4.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_lane[1].phy_txeq_i/TXEQ_PRECURSOR[4]_i_1__0/O
                         net (fo=33, routed)          1.322     5.487                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_lane[1].phy_txeq_i/TXEQ_PRECURSOR[4]_i_1__0_n_0
    SLICE_X94Y44         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_lane[1].phy_txeq_i/TXEQ_MAINCURSOR_reg[5]/CE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pipe_clk_1 rise edge)
                                                      4.000     4.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     4.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.046     4.046                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y43        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.329 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_pclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=1126, routed)        1.653     5.982                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_lane[1].phy_txeq_i/CLK_PCLK
    SLICE_X94Y44         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_lane[1].phy_txeq_i/TXEQ_MAINCURSOR_reg[5]/C
                         clock pessimism              0.128     6.110                           
                         clock uncertainty           -0.035     6.075                           
    SLICE_X94Y44         FDRE (Setup_EFF2_SLICEM_C_CE)
                                                     -0.050     6.025    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_lane[1].phy_txeq_i/TXEQ_MAINCURSOR_reg[5]
  -------------------------------------------------------------------
                         required time                          6.025                           
                         arrival time                          -5.487                           
  -------------------------------------------------------------------
                         slack                                  0.538                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_lane_0_inst/pipe_stages_1.pipe_tx_data_q_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by pipe_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXDATA[4]
                            (rising edge-triggered cell GTHE3_CHANNEL clocked by pipe_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             pipe_clk_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (pipe_clk_1 rise@0.000ns - pipe_clk_1 rise@0.000ns)
  Data Path Delay:        0.292ns  (logic 0.048ns (16.438%)  route 0.244ns (83.562%))
  Logic Levels:           0  
  Clock Path Skew:        0.089ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.124ns
    Source Clock Delay      (SCD):    0.945ns
    Clock Pessimism Removal (CPR):    0.090ns
  Clock Net Delay (Source):      0.827ns (routing 0.317ns, distribution 0.510ns)
  Clock Net Delay (Destination): 0.959ns (routing 0.360ns, distribution 0.599ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock pipe_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.018     0.018                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y43        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_pclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=1126, routed)        0.827     0.945                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_lane_0_inst/CLK_PCLK
    SLICE_X99Y49         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_lane_0_inst/pipe_stages_1.pipe_tx_data_q_reg[4]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X99Y49         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.048     0.993 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_lane_0_inst/pipe_stages_1.pipe_tx_data_q_reg[4]/Q
                         net (fo=1, routed)           0.244     1.237                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/GTHE3_CHANNEL_TXDATA[100]
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                                r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXDATA[4]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pipe_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.035     0.035                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y43        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_pclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=1126, routed)        0.959     1.124                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/CLK_PCLK
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                                r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2
                         clock pessimism             -0.090     1.034                           
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL (Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[4])
                                                      0.172     1.206    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST
  -------------------------------------------------------------------
                         required time                         -1.206                           
                         arrival time                           1.237                           
  -------------------------------------------------------------------
                         slack                                  0.031                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pipe_clk_1
Waveform(ns):       { 0.000 2.000 }
Period(ns):         4.000
Sources:            { nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_pclk/O }

Check Type        Corner  Lib Pin                 Reference Pin     Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     PCIE_3_1/PIPECLK        n/a               4.000         4.000       0.000      PCIE_3_1_X0Y0       nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/PIPECLK
Low Pulse Width   Slow    GTHE3_CHANNEL/RXUSRCLK  n/a               1.100         2.000       0.900      GTHE3_CHANNEL_X0Y7  nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
High Pulse Width  Slow    GTHE3_CHANNEL/RXUSRCLK  n/a               1.100         2.000       0.900      GTHE3_CHANNEL_X0Y7  nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Max Skew          Fast    PCIE_3_1/PIPECLK        PCIE_3_1/USERCLK  0.374         0.221       0.153      PCIE_3_1_X0Y0       nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst/PIPECLK



---------------------------------------------------------------------------------------------------
From Clock:  qclkp
  To Clock:  qclkp

Setup :            0  Failing Endpoints,  Worst Slack        9.399ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.132ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             9.399ns  (required time - arrival time)
  Source:                 sc/rsys/inst/blk[0].x6.inst1/CLK
                            (rising edge-triggered cell SRLC32E clocked by qclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sc/rsys/inst/blk[0].x6.inst3/out_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by qclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             qclkp
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (qclkp rise@10.000ns - qclkp rise@0.000ns)
  Data Path Delay:        0.575ns  (logic 0.548ns (95.304%)  route 0.027ns (4.696%))
  Logic Levels:           0  
  Clock Path Skew:        -0.052ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.716ns = ( 12.716 - 10.000 ) 
    Source Clock Delay      (SCD):    3.219ns
    Clock Pessimism Removal (CPR):    0.451ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.436ns (routing 0.957ns, distribution 1.479ns)
  Clock Net Delay (Destination): 2.157ns (routing 0.870ns, distribution 1.287ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock qclkp rise edge)      0.000     0.000 r  
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r  qclkp (IN)
                         net (fo=0)                   0.000     0.000    sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r  sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468    sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r  sc/_clkp/O
    X2Y1 (CLOCK_ROOT)    net (fo=5, routed)           2.436     3.219    sc/rsys/inst/out_reg[0]
    SLICE_X50Y174        SRLC32E                                      r  sc/rsys/inst/blk[0].x6.inst1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y174        SRLC32E (Prop_A6LUT_SLICEM_CLK_Q)
                                                      0.548     3.767 r  sc/rsys/inst/blk[0].x6.inst1/Q
                         net (fo=1, routed)           0.027     3.794    sc/rsys/inst/blk[0].x6.inst3/q1_0
    SLICE_X50Y174        FDRE                                         r  sc/rsys/inst/blk[0].x6.inst3/out_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock qclkp rise edge)     10.000    10.000 r  
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r  qclkp (IN)
                         net (fo=0)                   0.000    10.000    sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230    10.230 r  sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046    10.276    sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283    10.559 r  sc/_clkp/O
    X2Y1 (CLOCK_ROOT)    net (fo=5, routed)           2.157    12.716    sc/rsys/inst/blk[0].x6.inst3/out_reg[0]_0
    SLICE_X50Y174        FDRE                                         r  sc/rsys/inst/blk[0].x6.inst3/out_reg[0]/C
                         clock pessimism              0.451    13.167    
                         clock uncertainty           -0.035    13.132    
    SLICE_X50Y174        FDRE (Setup_AFF2_SLICEM_C_D)
                                                      0.061    13.193    sc/rsys/inst/blk[0].x6.inst3/out_reg[0]
  -------------------------------------------------------------------
                         required time                         13.193    
                         arrival time                          -3.794    
  -------------------------------------------------------------------
                         slack                                  9.399    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.132ns  (arrival time - required time)
  Source:                 sc/rsys/inst/blk[0].x6.inst1/CLK
                            (rising edge-triggered cell SRLC32E clocked by qclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sc/rsys/inst/blk[0].x6.inst3/out_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by qclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             qclkp
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (qclkp rise@0.000ns - qclkp rise@0.000ns)
  Data Path Delay:        0.219ns  (logic 0.204ns (93.151%)  route 0.015ns (6.849%))
  Logic Levels:           0  
  Clock Path Skew:        0.031ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.747ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    0.297ns
  Clock Net Delay (Source):      1.117ns (routing 0.504ns, distribution 0.613ns)
  Clock Net Delay (Destination): 1.310ns (routing 0.566ns, distribution 0.744ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock qclkp rise edge)      0.000     0.000 r  
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r  qclkp (IN)
                         net (fo=0)                   0.000     0.000    sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r  sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202    sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r  sc/_clkp/O
    X2Y1 (CLOCK_ROOT)    net (fo=5, routed)           1.117     1.419    sc/rsys/inst/out_reg[0]
    SLICE_X50Y174        SRLC32E                                      r  sc/rsys/inst/blk[0].x6.inst1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y174        SRLC32E (Prop_A6LUT_SLICEM_CLK_Q)
                                                      0.204     1.623 r  sc/rsys/inst/blk[0].x6.inst1/Q
                         net (fo=1, routed)           0.015     1.638    sc/rsys/inst/blk[0].x6.inst3/q1_0
    SLICE_X50Y174        FDRE                                         r  sc/rsys/inst/blk[0].x6.inst3/out_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock qclkp rise edge)      0.000     0.000 r  
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r  qclkp (IN)
                         net (fo=0)                   0.000     0.000    sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r  sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307    sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r  sc/_clkp/O
    X2Y1 (CLOCK_ROOT)    net (fo=5, routed)           1.310     1.747    sc/rsys/inst/blk[0].x6.inst3/out_reg[0]_0
    SLICE_X50Y174        FDRE                                         r  sc/rsys/inst/blk[0].x6.inst3/out_reg[0]/C
                         clock pessimism             -0.297     1.450    
    SLICE_X50Y174        FDRE (Hold_AFF2_SLICEM_C_D)
                                                      0.056     1.506    sc/rsys/inst/blk[0].x6.inst3/out_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.506    
                         arrival time                           1.638    
  -------------------------------------------------------------------
                         slack                                  0.132    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         qclkp
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { qclkp }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFG_GT/I          n/a            1.379         10.000      8.621      BUFG_GT_X0Y53    sc/_clkp/I
Low Pulse Width   Slow    MMCME3_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCME3_ADV_X1Y0  sc/f_dcm/CLKIN1
High Pulse Width  Slow    MMCME3_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCME3_ADV_X1Y0  sc/f_dcm/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  f_fb
  To Clock:  f_fb

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        8.929ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         f_fb
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { sc/f_dcm/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     MMCME3_ADV/CLKFBOUT  n/a            1.071         10.000      8.929      MMCME3_ADV_X1Y0  sc/f_dcm/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  gclkf
  To Clock:  gclkf

Setup :            0  Failing Endpoints,  Worst Slack        0.149ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.016ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.020ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.149ns  (required time - arrival time)
  Source:                 core1/cor[2].p1.engi/agc/blkAvg_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Destination:            core1/cor[2].p1.engi/agc/ftmp1_reg/DSP_PREADD_DATA_INST/AD[25]
                            (rising edge-triggered cell DSP_PREADD_DATA clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             gclkf
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (gclkf rise@6.000ns - gclkf rise@0.000ns)
  Data Path Delay:        5.581ns  (logic 3.930ns (70.417%)  route 1.651ns (29.583%))
  Logic Levels:           10  (DSP_A_B_DATA=2 DSP_ALU=1 DSP_M_DATA=1 DSP_MULTIPLIER=1 DSP_OUTPUT=1 DSP_PREADD=1 DSP_PREADD_DATA=2 LUT6=1)
  Clock Path Skew:        -0.178ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.173ns = ( 12.173 - 6.000 ) 
    Source Clock Delay      (SCD):    6.489ns
    Clock Pessimism Removal (CPR):    0.138ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.096ns (routing 1.079ns, distribution 2.017ns)
  Clock Net Delay (Destination): 2.730ns (routing 0.991ns, distribution 1.739ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.354     3.137                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.906 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.404     3.310                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.393 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      3.096     6.489                         core1/cor[2].p1.engi/agc/gclkf[0]
    SLICE_X73Y216        FDRE                                         r  AG_cores             core1/cor[2].p1.engi/agc/blkAvg_reg[16]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X73Y216        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     6.603 f  AG_cores             core1/cor[2].p1.engi/agc/blkAvg_reg[16]/Q
                         net (fo=23, routed)          0.712     7.315                         core1/cor[2].p1.engi/agc/sel0[5]
    SLICE_X75Y207        LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.193     7.508 f  AG_cores             core1/cor[2].p1.engi/agc/fdu11_return0__0_i_4__1/O
                         net (fo=1, routed)           0.403     7.911                         core1/cor[2].p1.engi/agc/fdu11_return0__0/A[17]
    DSP48E2_X13Y82       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[17]_A2_DATA[17])
                                                      0.337     8.248 r  AG_cores             core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_A_B_DATA_INST/A2_DATA[17]
                         net (fo=1, routed)           0.000     8.248                         core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_A_B_DATA.A2_DATA<17>
    DSP48E2_X13Y82       DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[17]_A2A1[17])
                                                      0.155     8.403 r  AG_cores             core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_PREADD_DATA_INST/A2A1[17]
                         net (fo=1, routed)           0.000     8.403                         core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_PREADD_DATA.A2A1<17>
    DSP48E2_X13Y82       DSP_MULTIPLIER (Prop_DSP_MULTIPLIER_DSP48E2_A2A1[17]_U[36])
                                                      0.866     9.269 f  AG_cores             core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_MULTIPLIER_INST/U[36]
                         net (fo=1, routed)           0.000     9.269                         core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_MULTIPLIER.U<36>
    DSP48E2_X13Y82       DSP_M_DATA (Prop_DSP_M_DATA_DSP48E2_U[36]_U_DATA[36])
                                                      0.110     9.379 r  AG_cores             core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_M_DATA_INST/U_DATA[36]
                         net (fo=1, routed)           0.000     9.379                         core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_M_DATA.U_DATA<36>
    DSP48E2_X13Y82       DSP_ALU (Prop_DSP_ALU_DSP48E2_U_DATA[36]_ALU_OUT[36])
                                                      0.702    10.081 f  AG_cores             core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_ALU_INST/ALU_OUT[36]
                         net (fo=1, routed)           0.000    10.081                         core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_ALU.ALU_OUT<36>
    DSP48E2_X13Y82       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[36]_P[36])
                                                      0.193    10.274 r  AG_cores             core1/cor[2].p1.engi/agc/fdu11_return0__0/DSP_OUTPUT_INST/P[36]
                         net (fo=5, routed)           0.536    10.810                         core1/cor[2].p1.engi/agc/ftmp1_reg/A[25]
    DSP48E2_X13Y84       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[25]_A2_DATA[25])
                                                      0.337    11.147 f  AG_cores             core1/cor[2].p1.engi/agc/ftmp1_reg/DSP_A_B_DATA_INST/A2_DATA[25]
                         net (fo=1, routed)           0.000    11.147                         core1/cor[2].p1.engi/agc/ftmp1_reg/DSP_A_B_DATA.A2_DATA<25>
    DSP48E2_X13Y84       DSP_PREADD_DATA (Prop_DSP_PREADD_DATA_DSP48E2_A2_DATA[25]_PREADD_AB[25])
                                                      0.262    11.409 r  AG_cores             core1/cor[2].p1.engi/agc/ftmp1_reg/DSP_PREADD_DATA_INST/PREADD_AB[25]
                         net (fo=1, routed)           0.000    11.409                         core1/cor[2].p1.engi/agc/ftmp1_reg/DSP_PREADD_DATA.PREADD_AB<25>
    DSP48E2_X13Y84       DSP_PREADD (Prop_DSP_PREADD_DSP48E2_PREADD_AB[25]_AD[25])
                                                      0.661    12.070 r  AG_cores             core1/cor[2].p1.engi/agc/ftmp1_reg/DSP_PREADD_INST/AD[25]
                         net (fo=1, routed)           0.000    12.070                         core1/cor[2].p1.engi/agc/ftmp1_reg/DSP_PREADD.AD<25>
    DSP48E2_X13Y84       DSP_PREADD_DATA                              r  AG_cores             core1/cor[2].p1.engi/agc/ftmp1_reg/DSP_PREADD_DATA_INST/AD[25]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkf rise edge)      6.000     6.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     6.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     6.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     6.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     6.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.128     8.687                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     9.022 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.346     9.368                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     9.443 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      2.730    12.173                         core1/cor[2].p1.engi/agc/ftmp1_reg/CLK
    DSP48E2_X13Y84       DSP_PREADD_DATA                              r  AG_cores             core1/cor[2].p1.engi/agc/ftmp1_reg/DSP_PREADD_DATA_INST/CLK
                         clock pessimism              0.138    12.312                           
                         clock uncertainty           -0.068    12.243                           
    DSP48E2_X13Y84       DSP_PREADD_DATA (Setup_DSP_PREADD_DATA_DSP48E2_CLK_AD[25])
                                                     -0.024    12.219    AG_cores               core1/cor[2].p1.engi/agc/ftmp1_reg/DSP_PREADD_DATA_INST
  -------------------------------------------------------------------
                         required time                         12.219                           
                         arrival time                         -12.070                           
  -------------------------------------------------------------------
                         slack                                  0.149                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 core1/cor[5].p1.engi/ssr/c_seq/genblk1[43].inst/endWhile.fo/pN.dp/inst/blk[0].x6.inst0/CLK
                            (rising edge-triggered cell SRLC32E clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Destination:            core1/cor[5].p1.engi/ssr/c_seq/genblk1[43].inst/endWhile.fo/pN.dp/inst/blk[0].x6.inst1/D
                            (rising edge-triggered cell SRL16E clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             gclkf
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclkf rise@0.000ns - gclkf rise@0.000ns)
  Data Path Delay:        0.145ns  (logic 0.145ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.009ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.160ns
    Source Clock Delay      (SCD):    3.066ns
    Clock Pessimism Removal (CPR):    0.085ns
  Clock Net Delay (Source):      1.236ns (routing 0.526ns, distribution 0.710ns)
  Clock Net Delay (Destination): 1.446ns (routing 0.583ns, distribution 0.863ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.078     1.380                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.650 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.153     1.803                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.830 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      1.236     3.066                         core1/cor[5].p1.engi/ssr/c_seq/genblk1[43].inst/endWhile.fo/pN.dp/inst/gclkf[0]
    SLICE_X40Y9          SRLC32E                                      r  AG_cores             core1/cor[5].p1.engi/ssr/c_seq/genblk1[43].inst/endWhile.fo/pN.dp/inst/blk[0].x6.inst0/CLK
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X40Y9          SRLC32E (Prop_D6LUT_SLICEM_CLK_Q31)
                                                      0.145     3.211 r  AG_cores             core1/cor[5].p1.engi/ssr/c_seq/genblk1[43].inst/endWhile.fo/pN.dp/inst/blk[0].x6.inst0/Q31
                         net (fo=1, routed)           0.000     3.211                         core1/cor[5].p1.engi/ssr/c_seq/genblk1[43].inst/endWhile.fo/pN.dp/inst/c0
    SLICE_X40Y9          SRL16E                                       r  AG_cores             core1/cor[5].p1.engi/ssr/c_seq/genblk1[43].inst/endWhile.fo/pN.dp/inst/blk[0].x6.inst1/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.244     1.681                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.207     1.474 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.209     1.683                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.714 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      1.446     3.160                         core1/cor[5].p1.engi/ssr/c_seq/genblk1[43].inst/endWhile.fo/pN.dp/inst/gclkf[0]
    SLICE_X40Y9          SRL16E                                       r  AG_cores             core1/cor[5].p1.engi/ssr/c_seq/genblk1[43].inst/endWhile.fo/pN.dp/inst/blk[0].x6.inst1/CLK
                         clock pessimism             -0.085     3.075                           
    SLICE_X40Y9          SRL16E (Hold_C6LUT_SLICEM_CLK_D)
                                                      0.120     3.195    AG_cores               core1/cor[5].p1.engi/ssr/c_seq/genblk1[43].inst/endWhile.fo/pN.dp/inst/blk[0].x6.inst1
  -------------------------------------------------------------------
                         required time                         -3.195                           
                         arrival time                           3.211                           
  -------------------------------------------------------------------
                         slack                                  0.016                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gclkf
Waveform(ns):       { 0.000 3.000 }
Period(ns):         6.000
Sources:            { sc/f_dcm/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     RAMB18E2/CLKARDCLK  n/a            1.961         6.000       4.039      RAMB18_X4Y110  core1/cor[0].p1.engi/ddc/dly/ax_reg/CLKARDCLK
Low Pulse Width   Slow    RAMB18E2/CLKARDCLK  n/a            0.980         3.000       2.020      RAMB18_X4Y110  core1/cor[0].p1.engi/ddc/dly/ax_reg/CLKARDCLK
High Pulse Width  Slow    RAMB18E2/CLKARDCLK  n/a            0.980         3.000       2.020      RAMB18_X4Y110  core1/cor[0].p1.engi/ddc/dly/ax_reg/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  gclkf2
  To Clock:  gclkf2

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.621ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gclkf2
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.000
Sources:            { sc/f_dcm/CLKOUT1 }

Check Type  Corner  Lib Pin   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location     Pin
Min Period  n/a     BUFGCE/I  n/a            1.379         3.000       1.621      BUFGCE_X1Y0  sc/_clkf2/I



---------------------------------------------------------------------------------------------------
From Clock:  gclkv
  To Clock:  gclkv

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.121ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gclkv
Waveform(ns):       { 0.000 1.250 }
Period(ns):         2.500
Sources:            { sc/o_dcm/CLKOUT5 }

Check Type  Corner  Lib Pin   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period  n/a     BUFGCE/I  n/a            1.379         2.500       1.121      BUFGCE_X1Y50  sc/_clkv/I



---------------------------------------------------------------------------------------------------
From Clock:  gclkx
  To Clock:  gclkx

Setup :            0  Failing Endpoints,  Worst Slack        0.217ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.229ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.217ns  (required time - arrival time)
  Source:                 core1/kbus_reg[43]/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            core1/cor[7].ibus__reg[7][43]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (gclkx rise@4.167ns - gclkx rise@0.000ns)
  Data Path Delay:        3.722ns  (logic 0.116ns (3.117%)  route 3.606ns (96.883%))
  Logic Levels:           0  
  Clock Path Skew:        -0.229ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.378ns = ( 9.545 - 4.167 ) 
    Source Clock Delay      (SCD):    5.594ns
    Clock Pessimism Removal (CPR):    -0.013ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.128ns (routing 0.335ns, distribution 1.793ns)
  Clock Net Delay (Destination): 1.873ns (routing 0.309ns, distribution 1.564ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.128     5.594                         core1/ioclk
    SLICE_X47Y144        FDRE                                         r  AG_cores             core1/kbus_reg[43]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X47Y144        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.116     5.710 r  AG_cores             core1/kbus_reg[43]/Q
                         net (fo=8, routed)           3.606     9.316                         core1/kbus[43]
    SLICE_X74Y13         FDRE                                         r  AG_cores             core1/cor[7].ibus__reg[7][43]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      4.167     4.167 r                       
    GTHE3_COMMON_X0Y2                                 0.000     4.167 r                       qclkp (IN)
                         net (fo=0)                   0.000     4.167                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     4.397 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     4.443                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.726 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     6.890                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     7.225 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.372     7.597                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     7.672 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.873     9.545                         core1/ioclk
    SLICE_X74Y13         FDRE                                         r  AG_cores             core1/cor[7].ibus__reg[7][43]/C
                         clock pessimism             -0.013     9.532                           
                         clock uncertainty           -0.060     9.472                           
    SLICE_X74Y13         FDRE (Setup_EFF2_SLICEL_C_D)
                                                      0.061     9.533    AG_cores               core1/cor[7].ibus__reg[7][43]
  -------------------------------------------------------------------
                         required time                          9.533                           
                         arrival time                          -9.316                           
  -------------------------------------------------------------------
                         slack                                  0.217                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 core1/cor[3].ibus__reg[3][61]/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            core1/cor[3].p1.engi/agc/f_i/dps/dpw[1].sdr.inst/r32k.ram/DINBDIN[29]
                            (rising edge-triggered cell RAMB36E2 clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclkx rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.156ns  (logic 0.049ns (31.410%)  route 0.107ns (68.590%))
  Logic Levels:           0  
  Clock Path Skew:        0.097ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.823ns
    Source Clock Delay      (SCD):    2.733ns
    Clock Pessimism Removal (CPR):    -0.007ns
  Clock Net Delay (Source):      0.880ns (routing 0.127ns, distribution 0.753ns)
  Clock Net Delay (Destination): 1.096ns (routing 0.142ns, distribution 0.954ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.880     2.733                         core1/ioclk
    SLICE_X60Y79         FDRE                                         r  AG_cores             core1/cor[3].ibus__reg[3][61]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X60Y79         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.049     2.782 r  AG_cores             core1/cor[3].ibus__reg[3][61]/Q
                         net (fo=1, routed)           0.107     2.889                         core1/cor[3].p1.engi/agc/f_i/dps/dpw[1].sdr.inst/r32k.ram_1[29]
    RAMB36_X6Y15         RAMB36E2                                     r  AG_cores             core1/cor[3].p1.engi/agc/f_i/dps/dpw[1].sdr.inst/r32k.ram/DINBDIN[29]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.209     1.696                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.727 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.096     2.823                         core1/cor[3].p1.engi/agc/f_i/dps/dpw[1].sdr.inst/ioclk
    RAMB36_X6Y15         RAMB36E2                                     r  AG_cores             core1/cor[3].p1.engi/agc/f_i/dps/dpw[1].sdr.inst/r32k.ram/CLKBWRCLK
                         clock pessimism              0.007     2.830                           
    RAMB36_X6Y15         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[29])
                                                      0.029     2.859    AG_cores               core1/cor[3].p1.engi/agc/f_i/dps/dpw[1].sdr.inst/r32k.ram
  -------------------------------------------------------------------
                         required time                         -2.859                           
                         arrival time                           2.889                           
  -------------------------------------------------------------------
                         slack                                  0.030                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gclkx
Waveform(ns):       { 0.000 2.083 }
Period(ns):         4.167
Sources:            { sc/o_dcm/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RAMB18E2/CLKARDCLK  n/a            1.709         4.167       2.458      RAMB18_X5Y60  cif/ram/dpr/dpw[0].sdr.inst/r16k.ram/CLKARDCLK
Low Pulse Width   Slow    RAMB18E2/CLKARDCLK  n/a            0.854         2.083       1.229      RAMB18_X5Y60  cif/ram/dpr/dpw[0].sdr.inst/r16k.ram/CLKARDCLK
High Pulse Width  Slow    RAMB18E2/CLKARDCLK  n/a            0.854         2.083       1.229      RAMB18_X5Y60  cif/ram/dpr/dpw[0].sdr.inst/r16k.ram/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  gclky
  To Clock:  gclky

Setup :            0  Failing Endpoints,  Worst Slack        0.382ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.032ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.646ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.382ns  (required time - arrival time)
  Source:                 ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram/ADDRARDADDR[14]
                            (rising edge-triggered cell RAMB36E2 clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             gclky
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (gclky rise@5.000ns - gclky rise@0.000ns)
  Data Path Delay:        3.950ns  (logic 2.026ns (51.291%)  route 1.924ns (48.709%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.127ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.733ns = ( 9.733 - 5.000 ) 
    Source Clock Delay      (SCD):    4.942ns
    Clock Pessimism Removal (CPR):    0.082ns
  Clock Uncertainty:      0.061ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.307ns (routing 0.009ns, distribution 1.298ns)
  Clock Net Delay (Destination): 1.095ns (routing 0.009ns, distribution 1.086ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.307     4.942                         ppc/j1/ncr1.code/dpw[0].sdr.inst/bclk
    RAMB36_X6Y30         RAMB36E2                                     r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram/CLKBWRCLK
  -------------------------------------------------------------------    ----------------------------------------
    RAMB36_X6Y30         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[0])
                                                      1.402     6.344 r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram/DOUTBDOUT[0]
                         net (fo=14, routed)          0.946     7.290                         ppc/j1/ncr1.code/dpw[0].sdr.inst/DOBDO[0]
    SLICE_X56Y141        LUT3 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.194     7.484 r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram_i_51__1/O
                         net (fo=2, routed)           0.192     7.676                         ppc/j1/bstkc[8]
    SLICE_X55Y141        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.116     7.792 r  AG_dmac/AG_ppc       ppc/j1/r32k.ram_i_59__1/O
                         net (fo=1, routed)           0.000     7.792                         ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram_14[6]
    SLICE_X55Y141        CARRY8 (Prop_CARRY8_SLICEM_S[6]_CO[7])
                                                      0.181     7.973 r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram_i_3__10/CO[7]
                         net (fo=1, routed)           0.027     8.000                         ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram_i_3__10_n_0
    SLICE_X55Y142        CARRY8 (Prop_CARRY8_SLICEM_CI_O[1])
                                                      0.133     8.133 r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram_i_2__10/O[1]
                         net (fo=1, routed)           0.759     8.892                         ppc/j1/ncr1.code/dpw[0].sdr.inst/astkc[11]
    RAMB36_X6Y30         RAMB36E2                                     r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram/ADDRARDADDR[14]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclky rise edge)      5.000     5.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     5.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     5.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     5.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     5.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     5.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     7.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335     8.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356     8.414                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224     8.638 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.095     9.733                         ppc/j1/ncr1.code/dpw[0].sdr.inst/bclk
    RAMB36_X6Y30         RAMB36E2                                     r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram/CLKARDCLK
                         clock pessimism              0.082     9.815                           
                         clock uncertainty           -0.061     9.754                           
    RAMB36_X6Y30         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[14])
                                                     -0.480     9.274    AG_dmac/AG_ppc         ppc/j1/ncr1.code/dpw[0].sdr.inst/r32k.ram
  -------------------------------------------------------------------
                         required time                          9.274                           
                         arrival time                          -8.892                           
  -------------------------------------------------------------------
                         slack                                  0.382                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 ppc/j1/mwrbus_reg[30]/C
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            ppc/dsr/dpw[0].sdr.inst/r32k.ram/DINADIN[30]
                            (rising edge-triggered cell RAMB36E2 clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             gclky
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclky rise@0.000ns - gclky rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.049ns (26.486%)  route 0.136ns (73.514%))
  Logic Levels:           0  
  Clock Path Skew:        0.124ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.479ns
    Source Clock Delay      (SCD):    2.360ns
    Clock Pessimism Removal (CPR):    -0.005ns
  Clock Net Delay (Source):      0.527ns (routing 0.007ns, distribution 0.520ns)
  Clock Net Delay (Destination): 0.661ns (routing 0.008ns, distribution 0.653ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.154     1.813                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.020     1.833 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         0.527     2.360                         ppc/j1/bclk
    SLICE_X58Y141        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mwrbus_reg[30]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X58Y141        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.049     2.409 r  AG_dmac/AG_ppc       ppc/j1/mwrbus_reg[30]/Q
                         net (fo=2, routed)           0.136     2.545                         ppc/dsr/dpw[0].sdr.inst/r32k.ram_1[30]
    RAMB36_X6Y28         RAMB36E2                                     r  AG_dmac/AG_ppc       ppc/dsr/dpw[0].sdr.inst/r32k.ram/DINADIN[30]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.210     1.697                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.121     1.818 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         0.661     2.479                         ppc/dsr/dpw[0].sdr.inst/bclk
    RAMB36_X6Y28         RAMB36E2                                     r  AG_dmac/AG_ppc       ppc/dsr/dpw[0].sdr.inst/r32k.ram/CLKARDCLK
                         clock pessimism              0.005     2.484                           
    RAMB36_X6Y28         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[30])
                                                      0.029     2.513    AG_dmac/AG_ppc         ppc/dsr/dpw[0].sdr.inst/r32k.ram
  -------------------------------------------------------------------
                         required time                         -2.513                           
                         arrival time                           2.545                           
  -------------------------------------------------------------------
                         slack                                  0.032                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gclky
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { sc/o_dcm/CLKOUT3 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.709         5.000       3.291      RAMB36_X7Y28  dmac/ram/dpw[0].sdr.inst/r32k.ram/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.854         2.500       1.646      RAMB36_X7Y28  dmac/ram/dpw[0].sdr.inst/r32k.ram/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.854         2.500       1.646      RAMB36_X7Y28  dmac/ram/dpw[0].sdr.inst/r32k.ram/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  gclks
  To Clock:  gclks

Setup :            0  Failing Endpoints,  Worst Slack        3.664ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.033ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.725ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.664ns  (required time - arrival time)
  Source:                 niop/bnk/prc/j1/jdsp/dsp/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            niop/bnk/prc/j1/tsoff_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             gclks
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (gclks rise@10.000ns - gclks rise@0.000ns)
  Data Path Delay:        6.170ns  (logic 1.389ns (22.512%)  route 4.781ns (77.488%))
  Logic Levels:           7  (CARRY8=1 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.022ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.698ns = ( 15.698 - 10.000 ) 
    Source Clock Delay      (SCD):    5.852ns
    Clock Pessimism Removal (CPR):    0.132ns
  Clock Uncertainty:      0.061ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.353ns, distribution 1.864ns)
  Clock Net Delay (Destination): 2.060ns (routing 0.326ns, distribution 1.734ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.217     5.852                         niop/bnk/prc/j1/jdsp/dsp/CLK
    DSP48E2_X15Y75       DSP_OUTPUT                                   r  AG_nioprc            niop/bnk/prc/j1/jdsp/dsp/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    ----------------------------------------
    DSP48E2_X15Y75       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[2])
                                                      0.316     6.168 r  AG_nioprc            niop/bnk/prc/j1/jdsp/dsp/DSP_OUTPUT_INST/P[2]
                         net (fo=12, routed)          0.743     6.911                         niop/bnk/prc/j1/jdsp/P[2]
    SLICE_X81Y183        LUT3 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.176     7.087 r  AG_nioprc            niop/bnk/prc/j1/jdsp/r32k.ram_i_44/O
                         net (fo=87, routed)          1.720     8.807                         niop/bnk/prc/j1/jdsp/stka[2]
    SLICE_X92Y186        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.072     8.879 r  AG_nioprc            niop/bnk/prc/j1/jdsp/tsoff[4]_i_2/O
                         net (fo=5, routed)           0.579     9.458                         niop/bnk/prc/j1/jdsp/tsoff[4]_i_2_n_0
    SLICE_X94Y187        LUT5 (Prop_C5LUT_SLICEM_I2_O)
                                                      0.212     9.670 r  AG_nioprc            niop/bnk/prc/j1/jdsp/tsoff[7]_i_3/O
                         net (fo=4, routed)           0.468    10.138                         niop/bnk/prc/j1/jdsp/tsoff[7]_i_3_n_0
    SLICE_X91Y186        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.189    10.327 r  AG_nioprc            niop/bnk/prc/j1/jdsp/tsoff[7]_i_2/O
                         net (fo=3, routed)           0.377    10.704                         niop/bnk/prc/j1/jdsp/bc1_reg[5][5]
    SLICE_X94Y186        LUT4 (Prop_D5LUT_SLICEM_I3_O)
                                                      0.210    10.914 r  AG_nioprc            niop/bnk/prc/j1/jdsp/tsoff0_carry_i_1/O
                         net (fo=1, routed)           0.000    10.914                         niop/bnk/prc/j1/jdsp_n_176
    SLICE_X94Y186        CARRY8 (Prop_CARRY8_SLICEM_DI[3]_CO[3])
                                                      0.174    11.088 r  AG_nioprc            niop/bnk/prc/j1/tsoff0_carry/CO[3]
                         net (fo=3, routed)           0.252    11.340                         niop/bnk/prc/j1/tsoff0_carry_n_4
    SLICE_X94Y187        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.040    11.380 r  AG_nioprc            niop/bnk/prc/j1/tsoff[7]_i_1/O
                         net (fo=6, routed)           0.642    12.022                         niop/bnk/prc/j1/tsoff
    SLICE_X94Y187        FDRE                                         r  AG_nioprc            niop/bnk/prc/j1/tsoff_reg[1]/R
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclks rise edge)     10.000    10.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r                       qclkp (IN)
                         net (fo=0)                   0.000    10.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230    10.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046    10.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283    10.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164    12.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335    13.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356    13.414                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224    13.638 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.060    15.698                         niop/bnk/prc/j1/gclks
    SLICE_X94Y187        FDRE                                         r  AG_nioprc            niop/bnk/prc/j1/tsoff_reg[1]/C
                         clock pessimism              0.132    15.830                           
                         clock uncertainty           -0.061    15.769                           
    SLICE_X94Y187        FDRE (Setup_HFF_SLICEM_C_R)
                                                     -0.083    15.686    AG_nioprc              niop/bnk/prc/j1/tsoff_reg[1]
  -------------------------------------------------------------------
                         required time                         15.686                           
                         arrival time                         -12.022                           
  -------------------------------------------------------------------
                         slack                                  3.664                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_rx_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxprogdivreset_out_reg/D
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             gclks
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclks rise@0.000ns - gclks rise@0.000ns)
  Data Path Delay:        0.269ns  (logic 0.100ns (37.175%)  route 0.169ns (62.825%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.180ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.025ns
    Source Clock Delay      (SCD):    2.833ns
    Clock Pessimism Removal (CPR):    0.012ns
  Clock Net Delay (Source):      1.000ns (routing 0.135ns, distribution 0.865ns)
  Clock Net Delay (Destination): 1.207ns (routing 0.151ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.154     1.813                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.020     1.833 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        1.000     2.833                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gclks
    SLICE_X98Y60         FDRE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_rx_reg[0]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X98Y60         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.048     2.881 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/FSM_sequential_sm_reset_rx_reg[0]/Q
                         net (fo=15, routed)          0.153     3.034                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_rxcdrlock_inst/Q[0]
    SLICE_X99Y59         LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.052     3.086 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_rxcdrlock_inst/rxprogdivreset_out_i_1/O
                         net (fo=1, routed)           0.016     3.102                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/bit_synchronizer_rxcdrlock_inst_n_2
    SLICE_X99Y59         FDRE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxprogdivreset_out_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.210     1.697                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.121     1.818 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        1.207     3.025                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gclks
    SLICE_X99Y59         FDRE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxprogdivreset_out_reg/C
                         clock pessimism             -0.012     3.013                           
    SLICE_X99Y59         FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.056     3.069    AG_riop                riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/rxprogdivreset_out_reg
  -------------------------------------------------------------------
                         required time                         -3.069                           
                         arrival time                           3.102                           
  -------------------------------------------------------------------
                         slack                                  0.033                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gclks
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { sc/_clks/O }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location          Pin
Min Period        n/a     ICAPE3/CLK  n/a            4.875         10.000      5.125      CONFIG_SITE_X0Y0  ice3/CLK
Low Pulse Width   Slow    ICAPE3/CLK  n/a            2.275         5.000       2.725      CONFIG_SITE_X0Y0  ice3/CLK
High Pulse Width  Slow    ICAPE3/CLK  n/a            2.275         5.000       2.725      CONFIG_SITE_X0Y0  ice3/CLK



---------------------------------------------------------------------------------------------------
From Clock:  lclks
  To Clock:  lclks

Setup :            0  Failing Endpoints,  Worst Slack        3.980ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.055ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.332ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.980ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg/C
                            (rising edge-triggered cell FDRE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             lclks
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (lclks rise@10.000ns - lclks rise@0.000ns)
  Data Path Delay:        5.886ns  (logic 0.720ns (12.232%)  route 5.166ns (87.768%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        -0.127ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.670ns = ( 14.670 - 10.000 ) 
    Source Clock Delay      (SCD):    4.783ns
    Clock Pessimism Removal (CPR):    -0.014ns
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.957ns, distribution 1.437ns)
  Clock Net Delay (Destination): 2.164ns (routing 0.870ns, distribution 1.294ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock lclks rise edge)      0.000     0.000 r  
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r  qclkp (IN)
                         net (fo=0)                   0.000     0.000    sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r  sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468    sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r  sc/_clkp/O
    X2Y1 (CLOCK_ROOT)    net (fo=5, routed)           2.394     3.177    sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                     -0.231     2.946 r  sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         1.837     4.783    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/clk
    SLICE_X30Y154        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y154        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.117     4.900 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg/Q
                         net (fo=19, routed)          1.470     6.370    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ack_timeout
    SLICE_X33Y158        LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.131     6.501 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state[2]_i_2/O
                         net (fo=2, routed)           0.618     7.119    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[1]
    SLICE_X33Y157        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.040     7.159 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4/O
                         net (fo=2, routed)           0.644     7.803    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/in_normal_mode_reg_1
    SLICE_X33Y156        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.172     7.975 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/in_normal_mode_i_1/O
                         net (fo=23, routed)          1.357     9.332    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_0
    SLICE_X34Y153        LUT5 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.093     9.425 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b1/O
                         net (fo=1, routed)           1.026    10.451    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_26
    SLICE_X35Y153        LUT4 (Prop_F5LUT_SLICEM_I2_O)
                                                      0.167    10.618 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r[1]_i_1/O
                         net (fo=1, routed)           0.051    10.669    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r[1]_i_1_n_0
    SLICE_X35Y153        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock lclks rise edge)     10.000    10.000 r  
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r  qclkp (IN)
                         net (fo=0)                   0.000    10.000    sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230    10.230 r  sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046    10.276    sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283    10.559 r  sc/_clkp/O
    X2Y1 (CLOCK_ROOT)    net (fo=5, routed)           2.164    12.723    sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                      0.335    13.058 r  sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         1.612    14.670    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X35Y153        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/C
                         clock pessimism             -0.014    14.656    
                         clock uncertainty           -0.067    14.589    
    SLICE_X35Y153        FDCE (Setup_FFF2_SLICEM_C_D)
                                                      0.060    14.649    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]
  -------------------------------------------------------------------
                         required time                         14.649    
                         arrival time                         -10.669    
  -------------------------------------------------------------------
                         slack                                  3.980    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 mb/cnt/rcnt_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mb/cnt/rcnt_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             lclks
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (lclks rise@0.000ns - lclks rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.079ns (43.646%)  route 0.102ns (56.354%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.070ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.768ns
    Source Clock Delay      (SCD):    2.740ns
    Clock Pessimism Removal (CPR):    -0.042ns
  Clock Net Delay (Source):      0.887ns (routing 0.360ns, distribution 0.527ns)
  Clock Net Delay (Destination): 1.041ns (routing 0.400ns, distribution 0.641ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock lclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         0.167     1.826                         sc/lclks
    BUFGCE_X1Y51         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkm/O
    X1Y2 (CLOCK_ROOT)    net (fo=13, routed)          0.887     2.740                         mb/cnt/gclkms[1]
    SLICE_X32Y141        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/rcnt_reg[0]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X32Y141        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.048     2.788 r  AG_dmac/AG_mbcnt     mb/cnt/rcnt_reg[0]/Q
                         net (fo=8, routed)           0.087     2.875                         mb/cnt/rcnt_reg[0]
    SLICE_X30Y141        LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.031     2.906 r  AG_dmac/AG_mbcnt     mb/cnt/rcnt[5]_i_1/O
                         net (fo=1, routed)           0.015     2.921                         mb/cnt/p_0_in__2[5]
    SLICE_X30Y141        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/rcnt_reg[5]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock lclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         0.209     1.696                         sc/lclks
    BUFGCE_X1Y51         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.727 r                       sc/_clkm/O
    X1Y2 (CLOCK_ROOT)    net (fo=13, routed)          1.041     2.768                         mb/cnt/gclkms[1]
    SLICE_X30Y141        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/rcnt_reg[5]/C
                         clock pessimism              0.042     2.810                           
    SLICE_X30Y141        FDRE (Hold_BFF_SLICEM_C_D)
                                                      0.056     2.866    AG_dmac/AG_mbcnt       mb/cnt/rcnt_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.866                           
                         arrival time                           2.921                           
  -------------------------------------------------------------------
                         slack                                  0.055                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         lclks
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { sc/o_dcm/CLKOUT2 }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I    n/a            1.379         10.000      8.621      BUFGCE_X1Y51   sc/_clkm/I
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.668         5.000       4.332      SLICE_X35Y157  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.668         5.000       4.332      SLICE_X35Y157  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK



---------------------------------------------------------------------------------------------------
From Clock:  lclkz
  To Clock:  lclkz

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.954ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         lclkz
Waveform(ns):       { 0.000 1.667 }
Period(ns):         3.333
Sources:            { sc/o_dcm/CLKOUT4 }

Check Type  Corner  Lib Pin   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period  n/a     BUFGCE/I  n/a            1.379         3.333       1.954      BUFGCE_X1Y48  sc/_clkz/I



---------------------------------------------------------------------------------------------------
From Clock:  rclkp
  To Clock:  rclkp

Setup :            0  Failing Endpoints,  Worst Slack        4.586ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.036ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.925ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.586ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/data_out_reg/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/master_watchdog_reg[24]/R
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.400ns  (rclkp rise@6.400ns - rclkp rise@0.000ns)
  Data Path Delay:        1.508ns  (logic 0.160ns (10.610%)  route 1.348ns (89.390%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.187ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.076ns = ( 8.476 - 6.400 ) 
    Source Clock Delay      (SCD):    2.533ns
    Clock Pessimism Removal (CPR):    0.271ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.778ns (routing 0.489ns, distribution 1.289ns)
  Clock Net Delay (Destination): 1.543ns (routing 0.441ns, distribution 1.102ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.358     0.358 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.082     0.440                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.755 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.778     2.533                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/CLK
    SLICE_X94Y189        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/data_out_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X94Y189        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.117     2.650 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/data_out_reg/Q
                         net (fo=1, routed)           0.662     3.312                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/block_lock_coreclk
    SLICE_X94Y170        LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.043     3.355 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/master_watchdog[0]_i_1__2/O
                         net (fo=29, routed)          0.686     4.041                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/master_watchdog0
    SLICE_X96Y176        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/master_watchdog_reg[24]/R
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      6.400     6.400 r                       
    GTHE3_COMMON_X0Y1                                 0.000     6.400 r                       rclkp (IN)
                         net (fo=0)                   0.000     6.400                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.204     6.604 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.046     6.650                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.933 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.543     8.476                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/CLK
    SLICE_X96Y176        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/master_watchdog_reg[24]/C
                         clock pessimism              0.271     8.746                           
                         clock uncertainty           -0.035     8.711                           
    SLICE_X96Y176        FDRE (Setup_AFF_SLICEL_C_R)
                                                     -0.084     8.627    AG_niop                niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/master_watchdog_reg[24]
  -------------------------------------------------------------------
                         required time                          8.627                           
                         arrival time                          -4.041                           
  -------------------------------------------------------------------
                         slack                                  4.586                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_rising_reg/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/gt0_gtrxreset_i_reg/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rclkp rise@0.000ns - rclkp rise@0.000ns)
  Data Path Delay:        0.167ns  (logic 0.079ns (47.305%)  route 0.088ns (52.695%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.075ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.344ns
    Source Clock Delay      (SCD):    1.054ns
    Clock Pessimism Removal (CPR):    0.216ns
  Clock Net Delay (Source):      0.775ns (routing 0.252ns, distribution 0.523ns)
  Clock Net Delay (Destination): 0.931ns (routing 0.289ns, distribution 0.642ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.161     0.161 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.018     0.179                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.279 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.775     1.054                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/CLK
    SLICE_X97Y173        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_rising_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X97Y173        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.048     1.102 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_rising_reg/Q
                         net (fo=1, routed)           0.072     1.174                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_rising
    SLICE_X95Y173        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.031     1.205 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/gt0_gtrxreset_i_i_1/O
                         net (fo=1, routed)           0.016     1.221                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/gt0_gtrxreset_c
    SLICE_X95Y173        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/gt0_gtrxreset_i_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.248     0.248 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.035     0.283                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.413 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.931     1.344                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/CLK
    SLICE_X95Y173        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/gt0_gtrxreset_i_reg/C
                         clock pessimism             -0.216     1.129                           
    SLICE_X95Y173        FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.056     1.185    AG_niop                niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/gt0_gtrxreset_i_reg
  -------------------------------------------------------------------
                         required time                         -1.185                           
                         arrival time                           1.221                           
  -------------------------------------------------------------------
                         slack                                  0.036                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         rclkp
Waveform(ns):       { 0.000 3.200 }
Period(ns):         6.400
Sources:            { rclkp }

Check Type        Corner  Lib Pin    Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFG_GT/I  n/a            1.379         6.400       5.021      BUFG_GT_X0Y38  niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/I
Low Pulse Width   Slow    FDRE/C     n/a            0.275         3.200       2.925      SLICE_X98Y134  niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_falling_reg/C
High Pulse Width  Slow    FDRE/C     n/a            0.275         3.200       2.925      SLICE_X98Y134  niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_falling_reg/C



---------------------------------------------------------------------------------------------------
From Clock:  GTHE3_CHANNEL_RXOUTCLK[0]
  To Clock:  GTHE3_CHANNEL_RXOUTCLK[0]

Setup :            0  Failing Endpoints,  Worst Slack        0.271ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.033ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.486ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.271ns  (required time - arrival time)
  Source:                 hi/fab/vfa1/vcnt_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            hi/fab/vcnt_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             GTHE3_CHANNEL_RXOUTCLK[0]
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.267ns  (GTHE3_CHANNEL_RXOUTCLK[0] rise@4.267ns - GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        3.872ns  (logic 0.233ns (6.018%)  route 3.639ns (93.982%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.148ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.239ns = ( 6.506 - 4.267 ) 
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    0.195ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.185ns (routing 0.702ns, distribution 1.483ns)
  Clock Net Delay (Destination): 1.910ns (routing 0.637ns, distribution 1.273ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        2.185     2.582                         hi/fab/vfa1/rclk1[0]
    SLICE_X70Y153        FDCE                                         r  AG_riop              hi/fab/vfa1/vcnt_reg[8]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X70Y153        FDCE (Prop_BFF2_SLICEL_C_Q)
                                                      0.118     2.700 r  AG_riop              hi/fab/vfa1/vcnt_reg[8]/Q
                         net (fo=4, routed)           3.616     6.316                         hi/fab/vfa1/Q[4]
    SLICE_X72Y153        LUT5 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.115     6.431 r  AG_riop              hi/fab/vfa1/vcnt[8]_i_1__170/O
                         net (fo=1, routed)           0.023     6.454                         hi/fab/vfa1_n_7
    SLICE_X72Y153        FDRE                                         r  AG_riop              hi/fab/vcnt_reg[8]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      4.267     4.267 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     4.267 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     4.313                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.596 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.910     6.506                         hi/fab/rclk1[0]
    SLICE_X72Y153        FDRE                                         r  AG_riop              hi/fab/vcnt_reg[8]/C
                         clock pessimism              0.195     6.701                           
                         clock uncertainty           -0.035     6.666                           
    SLICE_X72Y153        FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.059     6.725    AG_riop                hi/fab/vcnt_reg[8]
  -------------------------------------------------------------------
                         required time                          6.725                           
                         arrival time                          -6.454                           
  -------------------------------------------------------------------
                         slack                                  0.271                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 hi/fab/vidat_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            hi/fab/dps/dpw[0].sdr.inst/r32k.ram/DINBDIN[6]
                            (rising edge-triggered cell RAMB36E2 clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             GTHE3_CHANNEL_RXOUTCLK[0]
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns - GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        0.186ns  (logic 0.049ns (26.344%)  route 0.137ns (73.656%))
  Logic Levels:           0  
  Clock Path Skew:        0.124ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.369ns
    Source Clock Delay      (SCD):    1.090ns
    Clock Pessimism Removal (CPR):    0.155ns
  Clock Net Delay (Source):      0.972ns (routing 0.371ns, distribution 0.601ns)
  Clock Net Delay (Destination): 1.204ns (routing 0.422ns, distribution 0.782ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        0.972     1.090                         hi/fab/rclk1[0]
    SLICE_X75Y133        FDRE                                         r  AG_riop              hi/fab/vidat_reg[6]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X75Y133        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.049     1.139 r  AG_riop              hi/fab/vidat_reg[6]/Q
                         net (fo=1, routed)           0.137     1.276                         hi/fab/dps/dpw[0].sdr.inst/r32k.ram_0[6]
    RAMB36_X7Y26         RAMB36E2                                     r  AG_riop              hi/fab/dps/dpw[0].sdr.inst/r32k.ram/DINBDIN[6]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.204     1.369                         hi/fab/dps/dpw[0].sdr.inst/rclk1[0]
    RAMB36_X7Y26         RAMB36E2                                     r  AG_riop              hi/fab/dps/dpw[0].sdr.inst/r32k.ram/CLKBWRCLK
                         clock pessimism             -0.155     1.214                           
    RAMB36_X7Y26         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[6])
                                                      0.029     1.243    AG_riop                hi/fab/dps/dpw[0].sdr.inst/r32k.ram
  -------------------------------------------------------------------
                         required time                         -1.243                           
                         arrival time                           1.276                           
  -------------------------------------------------------------------
                         slack                                  0.033                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         GTHE3_CHANNEL_RXOUTCLK[0]
Waveform(ns):       { 0.000 2.133 }
Period(ns):         4.267
Sources:            { riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin            Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTHE3_CHANNEL/RXUSRCLK  n/a                      1.954         4.267       2.313      GTHE3_CHANNEL_X0Y0  riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Low Pulse Width   Slow    GTHE3_CHANNEL/RXUSRCLK  n/a                      0.880         2.133       1.253      GTHE3_CHANNEL_X0Y0  riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
High Pulse Width  Slow    GTHE3_CHANNEL/RXUSRCLK  n/a                      0.880         2.133       1.253      GTHE3_CHANNEL_X0Y0  riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Max Skew          Slow    GTHE3_CHANNEL/RXUSRCLK  GTHE3_CHANNEL/RXUSRCLK2  0.516         0.030       0.486      GTHE3_CHANNEL_X0Y0  riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK



---------------------------------------------------------------------------------------------------
From Clock:  GTHE3_CHANNEL_TXOUTCLK[0]
  To Clock:  GTHE3_CHANNEL_TXOUTCLK[0]

Setup :            0  Failing Endpoints,  Worst Slack        0.304ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.038ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.486ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.304ns  (required time - arrival time)
  Source:                 ho/fab/wfa1/vcnt_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            ho/fab/wfa1/vdif_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             GTHE3_CHANNEL_TXOUTCLK[0]
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.267ns  (GTHE3_CHANNEL_TXOUTCLK[0] rise@4.267ns - GTHE3_CHANNEL_TXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        3.915ns  (logic 0.330ns (8.429%)  route 3.585ns (91.571%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.074ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.328ns = ( 6.595 - 4.267 ) 
    Source Clock Delay      (SCD):    2.662ns
    Clock Pessimism Removal (CPR):    0.260ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.265ns (routing 0.707ns, distribution 1.558ns)
  Clock Net Delay (Destination): 1.999ns (routing 0.642ns, distribution 1.357ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         2.265     2.662                         ho/fab/wfa1/rclk1__0[0]
    SLICE_X77Y138        FDCE                                         r  AG_riop              ho/fab/wfa1/vcnt_reg[8]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X77Y138        FDCE (Prop_BFF2_SLICEL_C_Q)
                                                      0.118     2.780 r  AG_riop              ho/fab/wfa1/vcnt_reg[8]/Q
                         net (fo=4, routed)           3.549     6.329                         ho/fab/wfa1/vcnt_reg[8]_0[8]
    SLICE_X76Y140        LUT5 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.212     6.541 r  AG_riop              ho/fab/wfa1/vdif[4]_i_1__19/O
                         net (fo=1, routed)           0.036     6.577                         ho/fab/wfa1/vdif[4]_i_1__19_n_0
    SLICE_X76Y140        FDRE                                         r  AG_riop              ho/fab/wfa1/vdif_reg[4]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      4.267     4.267 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     4.267 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     4.313                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.596 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         1.999     6.595                         ho/fab/wfa1/rclk1__0[0]
    SLICE_X76Y140        FDRE                                         r  AG_riop              ho/fab/wfa1/vdif_reg[4]/C
                         clock pessimism              0.260     6.855                           
                         clock uncertainty           -0.035     6.819                           
    SLICE_X76Y140        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.062     6.881    AG_riop                ho/fab/wfa1/vdif_reg[4]
  -------------------------------------------------------------------
                         required time                          6.881                           
                         arrival time                          -6.577                           
  -------------------------------------------------------------------
                         slack                                  0.304                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 riop/bnk1/scr/cnt1_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            riop/bnk1/scr/inst/ADDRARDADDR[13]
                            (rising edge-triggered cell RAMB36E2 clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             GTHE3_CHANNEL_TXOUTCLK[0]
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (GTHE3_CHANNEL_TXOUTCLK[0] rise@0.000ns - GTHE3_CHANNEL_TXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        0.151ns  (logic 0.048ns (31.788%)  route 0.103ns (68.212%))
  Logic Levels:           0  
  Clock Path Skew:        0.136ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.443ns
    Source Clock Delay      (SCD):    1.145ns
    Clock Pessimism Removal (CPR):    0.162ns
  Clock Net Delay (Source):      1.027ns (routing 0.373ns, distribution 0.654ns)
  Clock Net Delay (Destination): 1.278ns (routing 0.423ns, distribution 0.855ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         1.027     1.145                         riop/bnk1/scr/inst_0
    SLICE_X90Y99         FDRE                                         r  AG_riop              riop/bnk1/scr/cnt1_reg[8]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X90Y99         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.048     1.193 r  AG_riop              riop/bnk1/scr/cnt1_reg[8]/Q
                         net (fo=2, routed)           0.103     1.296                         riop/bnk1/scr/cnt1_reg[8]
    RAMB36_X9Y19         RAMB36E2                                     r  AG_riop              riop/bnk1/scr/inst/ADDRARDADDR[13]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         1.278     1.443                         riop/bnk1/scr/inst_0
    RAMB36_X9Y19         RAMB36E2                                     r  AG_riop              riop/bnk1/scr/inst/CLKARDCLK
                         clock pessimism             -0.162     1.281                           
    RAMB36_X9Y19         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[13])
                                                     -0.023     1.258    AG_riop                riop/bnk1/scr/inst
  -------------------------------------------------------------------
                         required time                         -1.258                           
                         arrival time                           1.296                           
  -------------------------------------------------------------------
                         slack                                  0.038                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         GTHE3_CHANNEL_TXOUTCLK[0]
Waveform(ns):       { 0.000 2.133 }
Period(ns):         4.267
Sources:            { riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin            Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTHE3_CHANNEL/TXUSRCLK  n/a                      1.954         4.267       2.313      GTHE3_CHANNEL_X0Y0  riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK
Low Pulse Width   Slow    GTHE3_CHANNEL/TXUSRCLK  n/a                      0.880         2.133       1.253      GTHE3_CHANNEL_X0Y0  riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK
High Pulse Width  Slow    GTHE3_CHANNEL/TXUSRCLK  n/a                      0.880         2.133       1.253      GTHE3_CHANNEL_X0Y0  riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK
Max Skew          Slow    GTHE3_CHANNEL/TXUSRCLK  GTHE3_CHANNEL/TXUSRCLK2  0.516         0.030       0.486      GTHE3_CHANNEL_X0Y0  riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK



---------------------------------------------------------------------------------------------------
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :            0  Failing Endpoints,  Worst Slack        0.086ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.471ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.086ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].p2d/by_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].p2d/opkt_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@3.200ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        2.990ns  (logic 1.151ns (38.495%)  route 1.839ns (61.505%))
  Logic Levels:           9  (CARRY8=4 LUT4=2 LUT6=3)
  Clock Path Skew:        -0.149ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.377ns = ( 5.577 - 3.200 ) 
    Source Clock Delay      (SCD):    2.723ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.326ns (routing 0.623ns, distribution 1.703ns)
  Clock Net Delay (Destination): 2.048ns (routing 0.567ns, distribution 1.481ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.326     2.723                         niop/bnk/genblk2[0].genblk1[2].p2d/txusrclk2
    SLICE_X96Y255        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/by_reg[21]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y255        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.117     2.840 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/by_reg[21]/Q
                         net (fo=3, routed)           0.378     3.218                         niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[162].inst/If.fd/inq_reg[0]_0[10]
    SLICE_X96Y255        LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.132     3.350 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[162].inst/If.fd/inq[0]_i_6__23/O
                         net (fo=1, routed)           0.187     3.537                         niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[162].inst/If.fd/inq[0]_i_6__23_n_0
    SLICE_X97Y255        LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.071     3.608 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[162].inst/If.fd/inq[0]_i_2__150/O
                         net (fo=8, routed)           0.273     3.881                         niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/inq_reg[0]_6
    SLICE_X96Y252        LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.072     3.953 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/inq[0]_i_8__21/O
                         net (fo=1, routed)           0.214     4.167                         niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/c_xn[139]_230
    SLICE_X96Y249        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.131     4.298 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/inq[0]_i_3__28/O
                         net (fo=39, routed)          0.161     4.459                         niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/alleth_reg
    SLICE_X96Y247        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.040     4.499 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/inq[0]_i_1__798/O
                         net (fo=5, routed)           0.504     5.003                         niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/DI[0]
    SLICE_X95Y250        CARRY8 (Prop_CARRY8_SLICEL_DI[0]_CO[7])
                                                      0.364     5.367 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/opkt_reg[0]_i_2__1/CO[7]
                         net (fo=1, routed)           0.027     5.394                         niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/opkt_reg[0]_i_2__1_n_0
    SLICE_X95Y251        CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.019     5.413 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/opkt_reg[8]_i_1__1/CO[7]
                         net (fo=1, routed)           0.027     5.440                         niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/opkt_reg[8]_i_1__1_n_0
    SLICE_X95Y252        CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.019     5.459 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/opkt_reg[16]_i_1__1/CO[7]
                         net (fo=1, routed)           0.027     5.486                         niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/opkt_reg[16]_i_1__1_n_0
    SLICE_X95Y253        CARRY8 (Prop_CARRY8_SLICEL_CI_O[7])
                                                      0.186     5.672 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/c_seq/genblk1[52].inst/If.fd/pN.dp/inst/opkt_reg[24]_i_1__1/O[7]
                         net (fo=1, routed)           0.041     5.713                         niop/bnk/genblk2[0].genblk1[2].p2d/c_seq_n_311
    SLICE_X95Y253        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/opkt_reg[31]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.048     5.577                         niop/bnk/genblk2[0].genblk1[2].p2d/txusrclk2
    SLICE_X95Y253        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/opkt_reg[31]/C
                         clock pessimism              0.197     5.774                           
                         clock uncertainty           -0.035     5.739                           
    SLICE_X95Y253        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.060     5.799    AG_niop                niop/bnk/genblk2[0].genblk1[2].p2d/opkt_reg[31]
  -------------------------------------------------------------------
                         required time                          5.799                           
                         arrival time                          -5.713                           
  -------------------------------------------------------------------
                         slack                                  0.086                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].p2d/counts_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].p2d/c_wbus_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.171ns  (logic 0.079ns (46.199%)  route 0.092ns (53.801%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.085ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.457ns
    Source Clock Delay      (SCD):    1.215ns
    Clock Pessimism Removal (CPR):    0.157ns
  Clock Net Delay (Source):      1.097ns (routing 0.339ns, distribution 0.758ns)
  Clock Net Delay (Destination): 1.292ns (routing 0.384ns, distribution 0.908ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.097     1.215                         niop/bnk/genblk2[0].genblk1[3].p2d/txusrclk2
    SLICE_X93Y265        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/counts_reg[4]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X93Y265        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.049     1.264 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/counts_reg[4]/Q
                         net (fo=1, routed)           0.076     1.340                         niop/bnk/genblk2[0].genblk1[3].p2d/c_seq/genblk1[191].inst/other.fo/counts[4]
    SLICE_X94Y265        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.030     1.370 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/c_seq/genblk1[191].inst/other.fo/c_wbus[4]_i_1__26/O
                         net (fo=1, routed)           0.016     1.386                         niop/bnk/genblk2[0].genblk1[3].p2d/c_seq_n_177
    SLICE_X94Y265        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/c_wbus_reg[4]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.292     1.457                         niop/bnk/genblk2[0].genblk1[3].p2d/txusrclk2
    SLICE_X94Y265        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/c_wbus_reg[4]/C
                         clock pessimism             -0.157     1.300                           
    SLICE_X94Y265        FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.056     1.356    AG_niop                niop/bnk/genblk2[0].genblk1[3].p2d/c_wbus_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.356                           
                         arrival time                           1.386                           
  -------------------------------------------------------------------
                         slack                                  0.030                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
Waveform(ns):       { 0.000 1.600 }
Period(ns):         3.200
Sources:            { niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin            Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTHE3_CHANNEL/TXUSRCLK  n/a                      1.954         3.200       1.246      GTHE3_CHANNEL_X0Y8  niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK
Low Pulse Width   Slow    GTHE3_CHANNEL/TXUSRCLK  n/a                      0.880         1.600       0.720      GTHE3_CHANNEL_X0Y8  niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK
High Pulse Width  Slow    GTHE3_CHANNEL/TXUSRCLK  n/a                      0.880         1.600       0.720      GTHE3_CHANNEL_X0Y8  niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK
Max Skew          Slow    GTHE3_CHANNEL/TXUSRCLK  GTHE3_CHANNEL/TXUSRCLK2  0.516         0.045       0.471      GTHE3_CHANNEL_X0Y8  niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK



---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk
  To Clock:  rxoutclk

Setup :            0  Failing Endpoints,  Worst Slack        0.297ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.036ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.486ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.297ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].nolabel_line376/dp/dpr/dpw[0].sdr.inst/r16k.ram/WEBWE[2]
                            (rising edge-triggered cell RAMB18E2 clocked by rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk rise@3.200ns - rxoutclk rise@0.000ns)
  Data Path Delay:        2.061ns  (logic 0.362ns (17.564%)  route 1.699ns (82.436%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        -0.218ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.117ns = ( 5.317 - 3.200 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.178ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.116ns (routing 0.560ns, distribution 1.556ns)
  Clock Net Delay (Destination): 1.788ns (routing 0.508ns, distribution 1.280ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        2.116     2.513                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rxusrclk2
    SLICE_X84Y129        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_reg[3]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X84Y129        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     2.627 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_ctrl_reg[3]/Q
                         net (fo=5, routed)           0.734     3.361                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/xgmii_rxc[3]
    SLICE_X83Y159        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.116     3.477 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/r16k.ram_i_4__3/O
                         net (fo=1, routed)           0.301     3.778                         niop/bnk/genblk2[0].genblk1[0].nolabel_line376/dp/dpr/dpw[0].sdr.inst/r16k.ram_4
    SLICE_X83Y159        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.132     3.910 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].nolabel_line376/dp/dpr/dpw[0].sdr.inst/r16k.ram_i_2__3/O
                         net (fo=12, routed)          0.664     4.574                         niop/bnk/genblk2[0].genblk1[0].nolabel_line376/dp/dpr/dpw[0].sdr.inst/WEBWE[0]
    RAMB18_X7Y65         RAMB18E2                                     r  AG_niop              niop/bnk/genblk2[0].genblk1[0].nolabel_line376/dp/dpr/dpw[0].sdr.inst/r16k.ram/WEBWE[2]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.788     5.317                         niop/bnk/genblk2[0].genblk1[0].nolabel_line376/dp/dpr/dpw[0].sdr.inst/clk
    RAMB18_X7Y65         RAMB18E2                                     r  AG_niop              niop/bnk/genblk2[0].genblk1[0].nolabel_line376/dp/dpr/dpw[0].sdr.inst/r16k.ram/CLKBWRCLK
                         clock pessimism              0.178     5.495                           
                         clock uncertainty           -0.035     5.460                           
    RAMB18_X7Y65         RAMB18E2 (Setup_RAMB18E2_U_RAMB181_CLKBWRCLK_WEBWE[2])
                                                     -0.589     4.871    AG_niop                niop/bnk/genblk2[0].genblk1[0].nolabel_line376/dp/dpr/dpw[0].sdr.inst/r16k.ram
  -------------------------------------------------------------------
                         required time                          4.871                           
                         arrival time                          -4.574                           
  -------------------------------------------------------------------
                         slack                                  0.297                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/FSM_sequential_mcp1_state_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_timer_125us_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk rise@0.000ns - rxoutclk rise@0.000ns)
  Data Path Delay:        0.252ns  (logic 0.078ns (30.952%)  route 0.174ns (69.048%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.160ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.379ns
    Source Clock Delay      (SCD):    1.126ns
    Clock Pessimism Removal (CPR):    0.093ns
  Clock Net Delay (Source):      1.008ns (routing 0.314ns, distribution 0.694ns)
  Clock Net Delay (Destination): 1.214ns (routing 0.360ns, distribution 0.854ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.008     1.126                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/rxusrclk2
    SLICE_X95Y121        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/FSM_sequential_mcp1_state_reg[2]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X95Y121        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.048     1.174 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/FSM_sequential_mcp1_state_reg[2]/Q
                         net (fo=20, routed)          0.158     1.332                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_state__0[2]
    SLICE_X93Y118        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.030     1.362 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_timer_125us[14]_i_1/O
                         net (fo=1, routed)           0.016     1.378                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_timer_125us[14]_i_1_n_0
    SLICE_X93Y118        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_timer_125us_reg[14]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.214     1.379                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/rxusrclk2
    SLICE_X93Y118        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_timer_125us_reg[14]/C
                         clock pessimism             -0.093     1.286                           
    SLICE_X93Y118        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.056     1.342    AG_niop                niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_timer_125us_reg[14]
  -------------------------------------------------------------------
                         required time                         -1.342                           
                         arrival time                           1.378                           
  -------------------------------------------------------------------
                         slack                                  0.036                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         rxoutclk
Waveform(ns):       { 0.000 1.600 }
Period(ns):         3.200
Sources:            { niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin            Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTHE3_CHANNEL/RXUSRCLK  n/a                      1.954         3.200       1.246      GTHE3_CHANNEL_X0Y8  niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Low Pulse Width   Slow    GTHE3_CHANNEL/RXUSRCLK  n/a                      0.880         1.600       0.720      GTHE3_CHANNEL_X0Y8  niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
High Pulse Width  Slow    GTHE3_CHANNEL/RXUSRCLK  n/a                      0.880         1.600       0.720      GTHE3_CHANNEL_X0Y8  niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Max Skew          Slow    GTHE3_CHANNEL/RXUSRCLK  GTHE3_CHANNEL/RXUSRCLK2  0.516         0.030       0.486      GTHE3_CHANNEL_X0Y8  niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK



---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk_1
  To Clock:  rxoutclk_1

Setup :            0  Failing Endpoints,  Worst Slack        0.323ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.036ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.486ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.323ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_1 rise@3.200ns - rxoutclk_1 rise@0.000ns)
  Data Path Delay:        2.736ns  (logic 0.868ns (31.725%)  route 1.868ns (68.275%))
  Logic Levels:           6  (LUT4=1 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.165ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.801ns = ( 5.001 - 3.200 ) 
    Source Clock Delay      (SCD):    2.119ns
    Clock Pessimism Removal (CPR):    0.153ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.722ns (routing 0.414ns, distribution 1.308ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.372ns, distribution 1.100ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.722     2.119                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rxusrclk2
    SLICE_X90Y158        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[9]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X90Y158        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.117     2.236 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[9]/Q
                         net (fo=18, routed)          0.588     2.824                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[7]
    SLICE_X92Y159        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.091     2.915 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_31/O
                         net (fo=3, routed)           0.406     3.321                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_31_n_0
    SLICE_X92Y159        LUT5 (Prop_G5LUT_SLICEL_I0_O)
                                                      0.092     3.413 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_27/O
                         net (fo=1, routed)           0.334     3.747                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_27_n_0
    SLICE_X92Y160        LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.131     3.878 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_7/O
                         net (fo=1, routed)           0.211     4.089                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_7_n_0
    SLICE_X93Y160        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.174     4.263 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_2/O
                         net (fo=3, routed)           0.233     4.496                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_2_n_0
    SLICE_X91Y158        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.131     4.627 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[1]_i_2/O
                         net (fo=1, routed)           0.069     4.696                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg__14[1]
    SLICE_X91Y158        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.132     4.828 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[1]_i_1/O
                         net (fo=1, routed)           0.027     4.855                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[1]_i_1_n_0
    SLICE_X91Y158        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[1]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_1 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.472     5.001                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rxusrclk2
    SLICE_X91Y158        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[1]/C
                         clock pessimism              0.153     5.154                           
                         clock uncertainty           -0.035     5.118                           
    SLICE_X91Y158        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.060     5.178    AG_niop                niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          5.178                           
                         arrival time                          -4.855                           
  -------------------------------------------------------------------
                         slack                                  0.323                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].e2p/tcnt_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].p2d/p_i/dps/dpw[0].sdr.inst/r16k.ram/DINADIN[7]
                            (rising edge-triggered cell RAMB18E2 clocked by rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_1 rise@0.000ns - rxoutclk_1 rise@0.000ns)
  Data Path Delay:        0.148ns  (logic 0.049ns (33.108%)  route 0.099ns (66.892%))
  Logic Levels:           0  
  Clock Path Skew:        0.083ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.126ns
    Source Clock Delay      (SCD):    0.886ns
    Clock Pessimism Removal (CPR):    0.157ns
  Clock Net Delay (Source):      0.768ns (routing 0.222ns, distribution 0.546ns)
  Clock Net Delay (Destination): 0.961ns (routing 0.256ns, distribution 0.705ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        0.768     0.886                         niop/bnk/genblk2[0].genblk1[1].e2p/CLK
    SLICE_X91Y226        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].e2p/tcnt_reg[5]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y226        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.049     0.935 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].e2p/tcnt_reg[5]/Q
                         net (fo=3, routed)           0.099     1.034                         niop/bnk/genblk2[0].genblk1[1].p2d/p_i/dps/dpw[0].sdr.inst/pbus[5]
    RAMB18_X9Y90         RAMB18E2                                     r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/p_i/dps/dpw[0].sdr.inst/r16k.ram/DINADIN[7]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        0.961     1.126                         niop/bnk/genblk2[0].genblk1[1].p2d/p_i/dps/dpw[0].sdr.inst/clk
    RAMB18_X9Y90         RAMB18E2                                     r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/p_i/dps/dpw[0].sdr.inst/r16k.ram/CLKBWRCLK
                         clock pessimism             -0.157     0.969                           
    RAMB18_X9Y90         RAMB18E2 (Hold_RAMB18E2_L_RAMB180_CLKBWRCLK_DINADIN[7])
                                                      0.029     0.998    AG_niop                niop/bnk/genblk2[0].genblk1[1].p2d/p_i/dps/dpw[0].sdr.inst/r16k.ram
  -------------------------------------------------------------------
                         required time                         -0.998                           
                         arrival time                           1.034                           
  -------------------------------------------------------------------
                         slack                                  0.036                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         rxoutclk_1
Waveform(ns):       { 0.000 1.600 }
Period(ns):         3.200
Sources:            { niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin            Required(ns)  Actual(ns)  Slack(ns)  Location            Pin
Min Period        n/a     GTHE3_CHANNEL/RXUSRCLK  n/a                      1.954         3.200       1.246      GTHE3_CHANNEL_X0Y9  niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Low Pulse Width   Slow    GTHE3_CHANNEL/RXUSRCLK  n/a                      0.880         1.600       0.720      GTHE3_CHANNEL_X0Y9  niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
High Pulse Width  Slow    GTHE3_CHANNEL/RXUSRCLK  n/a                      0.880         1.600       0.720      GTHE3_CHANNEL_X0Y9  niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Max Skew          Slow    GTHE3_CHANNEL/RXUSRCLK  GTHE3_CHANNEL/RXUSRCLK2  0.516         0.030       0.486      GTHE3_CHANNEL_X0Y9  niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK



---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk_2
  To Clock:  rxoutclk_2

Setup :            0  Failing Endpoints,  Worst Slack        0.545ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.035ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.486ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.545ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[56]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_2 rise@3.200ns - rxoutclk_2 rise@0.000ns)
  Data Path Delay:        2.553ns  (logic 1.072ns (41.990%)  route 1.481ns (58.010%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        -0.126ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.171ns = ( 5.371 - 3.200 ) 
    Source Clock Delay      (SCD):    2.480ns
    Clock Pessimism Removal (CPR):    0.183ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.083ns (routing 0.584ns, distribution 1.499ns)
  Clock Net Delay (Destination): 1.842ns (routing 0.527ns, distribution 1.315ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        2.083     2.480                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rxusrclk2
    SLICE_X98Y201        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[56]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X98Y201        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.114     2.594 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[56]/Q
                         net (fo=8, routed)           0.353     2.947                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/character0_in[4]
    SLICE_X97Y202        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.172     3.119 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_39/O
                         net (fo=1, routed)           0.248     3.367                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_39_n_0
    SLICE_X97Y202        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.172     3.539 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_21/O
                         net (fo=5, routed)           0.269     3.808                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_21_n_0
    SLICE_X99Y203        LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.175     3.983 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_6/O
                         net (fo=1, routed)           0.193     4.176                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_6_n_0
    SLICE_X99Y203        LUT5 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.130     4.306 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_2/O
                         net (fo=3, routed)           0.247     4.553                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_2_n_0
    SLICE_X100Y203       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.177     4.730 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[1]_i_2/O
                         net (fo=1, routed)           0.141     4.871                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg__14[1]
    SLICE_X100Y202       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.132     5.003 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[1]_i_1/O
                         net (fo=1, routed)           0.030     5.033                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[1]_i_1_n_0
    SLICE_X100Y202       FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[1]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.842     5.371                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rxusrclk2
    SLICE_X100Y202       FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[1]/C
                         clock pessimism              0.183     5.554                           
                         clock uncertainty           -0.035     5.519                           
    SLICE_X100Y202       FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.059     5.578    AG_niop                niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          5.578                           
                         arrival time                          -5.033                           
  -------------------------------------------------------------------
                         slack                                  0.545                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/FSM_sequential_mcp1_state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_ber_cnt_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_2 rise@0.000ns - rxoutclk_2 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.078ns (42.162%)  route 0.107ns (57.838%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.293ns
    Source Clock Delay      (SCD):    1.056ns
    Clock Pessimism Removal (CPR):    0.143ns
  Clock Net Delay (Source):      0.938ns (routing 0.304ns, distribution 0.634ns)
  Clock Net Delay (Destination): 1.128ns (routing 0.346ns, distribution 0.782ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        0.938     1.056                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/rxusrclk2
    SLICE_X100Y197       FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/FSM_sequential_mcp1_state_reg[1]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X100Y197       FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.048     1.104 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/FSM_sequential_mcp1_state_reg[1]/Q
                         net (fo=24, routed)          0.091     1.195                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_state__0[1]
    SLICE_X99Y197        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.030     1.225 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_ber_cnt[4]_i_2/O
                         net (fo=1, routed)           0.016     1.241                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_ber_cnt[4]_i_2_n_0
    SLICE_X99Y197        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_ber_cnt_reg[4]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.128     1.293                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/rxusrclk2
    SLICE_X99Y197        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_ber_cnt_reg[4]/C
                         clock pessimism             -0.143     1.150                           
    SLICE_X99Y197        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.056     1.206    AG_niop                niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_ber_mon_fsm_i/mcp1_ber_cnt_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.206                           
                         arrival time                           1.241                           
  -------------------------------------------------------------------
                         slack                                  0.035                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         rxoutclk_2
Waveform(ns):       { 0.000 1.600 }
Period(ns):         3.200
Sources:            { niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin            Required(ns)  Actual(ns)  Slack(ns)  Location             Pin
Min Period        n/a     GTHE3_CHANNEL/RXUSRCLK  n/a                      1.954         3.200       1.246      GTHE3_CHANNEL_X0Y10  niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Low Pulse Width   Slow    GTHE3_CHANNEL/RXUSRCLK  n/a                      0.880         1.600       0.720      GTHE3_CHANNEL_X0Y10  niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
High Pulse Width  Slow    GTHE3_CHANNEL/RXUSRCLK  n/a                      0.880         1.600       0.720      GTHE3_CHANNEL_X0Y10  niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Max Skew          Slow    GTHE3_CHANNEL/RXUSRCLK  GTHE3_CHANNEL/RXUSRCLK2  0.516         0.030       0.486      GTHE3_CHANNEL_X0Y10  niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK



---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk_3
  To Clock:  rxoutclk_3

Setup :            0  Failing Endpoints,  Worst Slack        0.562ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.033ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.479ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.562ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_3
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_3 rise@3.200ns - rxoutclk_3 rise@0.000ns)
  Data Path Delay:        2.594ns  (logic 1.223ns (47.147%)  route 1.371ns (52.853%))
  Logic Levels:           6  (LUT4=2 LUT5=2 LUT6=2)
  Clock Path Skew:        -0.071ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.111ns = ( 5.311 - 3.200 ) 
    Source Clock Delay      (SCD):    2.424ns
    Clock Pessimism Removal (CPR):    0.242ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.027ns (routing 0.575ns, distribution 1.452ns)
  Clock Net Delay (Destination): 1.782ns (routing 0.520ns, distribution 1.262ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_3 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        2.027     2.424                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rxusrclk2
    SLICE_X96Y234        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[6]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y234        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.114     2.538 f  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_66_enc_reg[6]/Q
                         net (fo=13, routed)          0.246     2.784                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field[4]
    SLICE_X94Y234        LUT4 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.212     2.996 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[2]_i_20/O
                         net (fo=2, routed)           0.316     3.312                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[2]_i_20_n_0
    SLICE_X94Y234        LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.191     3.503 f  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_13/O
                         net (fo=2, routed)           0.257     3.760                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/p_1_in5_in
    SLICE_X96Y234        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.172     3.932 f  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_4/O
                         net (fo=1, routed)           0.203     4.135                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/block_field_T
    SLICE_X96Y233        LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.185     4.320 f  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_2/O
                         net (fo=3, routed)           0.162     4.482                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[0]_i_2_n_0
    SLICE_X96Y235        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.189     4.671 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[2]_i_2/O
                         net (fo=1, routed)           0.142     4.813                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[2]_i_2_n_0
    SLICE_X97Y235        LUT4 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.160     4.973 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[2]_i_1/O
                         net (fo=1, routed)           0.045     5.018                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg[2]_i_1_n_0
    SLICE_X97Y235        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_3 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.782     5.311                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rxusrclk2
    SLICE_X97Y235        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[2]/C
                         clock pessimism              0.242     5.553                           
                         clock uncertainty           -0.035     5.518                           
    SLICE_X97Y235        FDRE (Setup_BFF2_SLICEL_C_D)
                                                      0.062     5.580    AG_niop                niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_r_type_next_reg_reg[2]
  -------------------------------------------------------------------
                         required time                          5.580                           
                         arrival time                          -5.018                           
  -------------------------------------------------------------------
                         slack                                  0.562                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_rx_64_data_out_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_3
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_3 rise@0.000ns - rxoutclk_3 rise@0.000ns)
  Data Path Delay:        0.150ns  (logic 0.064ns (42.667%)  route 0.086ns (57.333%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.210ns
    Source Clock Delay      (SCD):    1.004ns
    Clock Pessimism Removal (CPR):    0.145ns
  Clock Net Delay (Source):      0.886ns (routing 0.302ns, distribution 0.584ns)
  Clock Net Delay (Destination): 1.045ns (routing 0.345ns, distribution 0.700ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_3 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        0.886     1.004                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rxusrclk2
    SLICE_X92Y234        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_rx_64_data_out_reg[16]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X92Y234        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.049     1.053 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_rx_64_data_out_reg[16]/Q
                         net (fo=1, routed)           0.070     1.123                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/mcp1_rx_64_data_out[16]
    SLICE_X91Y234        LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.015     1.138 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_decoder_i/rx_ebuff_data[16]_i_1/O
                         net (fo=1, routed)           0.016     1.154                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_reg[31]_0[16]
    SLICE_X91Y234        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_reg[16]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_3 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.045     1.210                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rxusrclk2
    SLICE_X91Y234        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_reg[16]/C
                         clock pessimism             -0.145     1.065                           
    SLICE_X91Y234        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.056     1.121    AG_niop                niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rx_ebuff_data_reg[16]
  -------------------------------------------------------------------
                         required time                         -1.121                           
                         arrival time                           1.154                           
  -------------------------------------------------------------------
                         slack                                  0.033                           





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         rxoutclk_3
Waveform(ns):       { 0.000 1.600 }
Period(ns):         3.200
Sources:            { niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin            Required(ns)  Actual(ns)  Slack(ns)  Location             Pin
Min Period        n/a     GTHE3_CHANNEL/RXUSRCLK  n/a                      1.954         3.200       1.246      GTHE3_CHANNEL_X0Y11  niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Low Pulse Width   Slow    GTHE3_CHANNEL/RXUSRCLK  n/a                      0.880         1.600       0.720      GTHE3_CHANNEL_X0Y11  niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
High Pulse Width  Slow    GTHE3_CHANNEL/RXUSRCLK  n/a                      0.880         1.600       0.720      GTHE3_CHANNEL_X0Y11  niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK
Max Skew          Slow    GTHE3_CHANNEL/RXUSRCLK  GTHE3_CHANNEL/RXUSRCLK2  0.516         0.037       0.479      GTHE3_CHANNEL_X0Y11  niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        1.731ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.731ns  (required time - arrival time)
  Source:                 mb/mig/inst/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@4.000ns period=7.999ns})
  Destination:            mb/mig/inst/u_io_addr_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.332ns  (logic 0.118ns (8.859%)  route 1.214ns (91.141%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X9Y162                                      0.000     0.000 r  AG_mb                mb/mig/inst/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
    SLICE_X9Y162         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.118     0.118 r  AG_mb                mb/mig/inst/u_ddr_cal_riu/io_address_riuclk_reg[4]/Q
                         net (fo=42, routed)          1.214     1.332                         mb/mig/inst/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[4]
    SLICE_X14Y148        FDRE                                         r  AG_mb                mb/mig/inst/u_io_addr_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    3.000     3.000                         
    SLICE_X14Y148        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.063     3.063    AG_mb                  mb/mig/inst/u_io_addr_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.063                           
                         arrival time                          -1.332                           
  -------------------------------------------------------------------
                         slack                                  1.731                           





---------------------------------------------------------------------------------------------------
From Clock:  gclkx
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        3.189ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.041ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.189ns  (required time - arrival time)
  Source:                 mb/cnt/qslot/aw_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            mb/cnt/qslot/dd/rb[0].cr/DP/WADR3
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.534ns  (logic 0.118ns (4.657%)  route 2.416ns (95.343%))
  Logic Levels:           0  
  Clock Path Skew:        0.176ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.812ns
    Source Clock Delay      (SCD):    5.636ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.240ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.205ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      2.170ns (routing 0.335ns, distribution 1.835ns)
  Clock Net Delay (Destination): 1.806ns (routing 0.309ns, distribution 1.497ns)
  Timing Exception:       MaxDelay Path 6.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.170     5.636                         mb/cnt/qslot/ioclk
    SLICE_X30Y150        FDRE                                         r  AG_mb/AG_mbasync     mb/cnt/qslot/aw_reg[3]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X30Y150        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.118     5.754 r  AG_mb/AG_mbasync     mb/cnt/qslot/aw_reg[3]/Q
                         net (fo=12, routed)          2.416     8.170                         mb/cnt/qslot/dd/rb[0].cr/A3
    SLICE_X30Y150        RAMD32                                       r  AG_mb/AG_mbasync     mb/cnt/qslot/dd/rb[0].cr/DP/WADR3
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    6.000     6.000                         
    D23                                               0.000     6.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     6.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     6.353 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     6.404                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     6.404 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     7.053                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     7.128 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096     9.224                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     9.559 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.372     9.931                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075    10.006 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.806    11.812                         mb/cnt/qslot/dd/rb[0].cr/WCLK
    SLICE_X30Y150        RAMD32                                       r  AG_mb/AG_mbasync     mb/cnt/qslot/dd/rb[0].cr/DP/CLK
                         clock pessimism              0.000    11.812                           
                         clock uncertainty           -0.240    11.572                           
    SLICE_X30Y150        RAMD32 (Setup_G6LUT_SLICEM_CLK_WADR3)
                                                     -0.212    11.360    AG_mb/AG_mbasync       mb/cnt/qslot/dd/rb[0].cr/DP
  -------------------------------------------------------------------
                         required time                         11.360                           
                         arrival time                          -8.170                           
  -------------------------------------------------------------------
                         slack                                  3.189                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 mb/cnt/qslot/dw_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            mb/cnt/qslot/dd/rb[2].cr/DP/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.674ns  (logic 0.049ns (7.270%)  route 0.625ns (92.730%))
  Logic Levels:           0  
  Clock Path Skew:        0.331ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.083ns
    Source Clock Delay      (SCD):    2.752ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.240ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.205ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      0.899ns (routing 0.127ns, distribution 0.772ns)
  Clock Net Delay (Destination): 1.019ns (routing 0.142ns, distribution 0.877ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.899     2.752                         mb/cnt/qslot/ioclk
    SLICE_X29Y151        FDRE                                         r  AG_mb/AG_mbasync     mb/cnt/qslot/dw_reg[2]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X29Y151        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.049     2.801 r  AG_mb/AG_mbasync     mb/cnt/qslot/dw_reg[2]/Q
                         net (fo=2, routed)           0.625     3.426                         mb/cnt/qslot/dd/rb[2].cr/D
    SLICE_X30Y150        RAMD32                                       r  AG_mb/AG_mbasync     mb/cnt/qslot/dd/rb[2].cr/DP/I
  -------------------------------------------------------------------    ----------------------------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.396     0.397 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.048     0.445                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.445 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.409     0.854                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     0.885 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.146     2.031                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.207     1.824 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.209     2.033                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     2.064 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.019     3.083                         mb/cnt/qslot/dd/rb[2].cr/WCLK
    SLICE_X30Y150        RAMD32                                       r  AG_mb/AG_mbasync     mb/cnt/qslot/dd/rb[2].cr/DP/CLK
                         clock pessimism              0.000     3.083                           
                         clock uncertainty            0.240     3.323                           
    SLICE_X30Y150        RAMD32 (Hold_E6LUT_SLICEM_CLK_I)
                                                      0.062     3.385    AG_mb/AG_mbasync       mb/cnt/qslot/dd/rb[2].cr/DP
  -------------------------------------------------------------------
                         required time                         -3.385                           
                         arrival time                           3.426                           
  -------------------------------------------------------------------
                         slack                                  0.041                           





---------------------------------------------------------------------------------------------------
From Clock:  lclks
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        0.221ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.072ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.221ns  (required time - arrival time)
  Source:                 mb/cnt/needrefresh_reg/C
                            (rising edge-triggered cell FDRE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mb/cnt/needrefresha_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.600ns  (mmcm_clkout0 rise@3991.600ns - lclks rise@3990.000ns)
  Data Path Delay:        1.518ns  (logic 0.117ns (7.708%)  route 1.401ns (92.292%))
  Logic Levels:           0  
  Clock Path Skew:        0.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.802ns = ( 3997.402 - 3991.600 ) 
    Source Clock Delay      (SCD):    5.473ns = ( 3995.473 - 3990.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.248ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.223ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      2.007ns (routing 0.743ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.796ns (routing 0.309ns, distribution 1.487ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock lclks rise edge)   3990.000  3990.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000  3990.000 r                       qclkp (IN)
                         net (fo=0)                   0.000  3990.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386  3990.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082  3990.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315  3990.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394  3993.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                     -0.231  3992.946 r                       sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         0.437  3993.383                         sc/lclks
    BUFGCE_X1Y51         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083  3993.466 r                       sc/_clkm/O
    X1Y2 (CLOCK_ROOT)    net (fo=13, routed)          2.007  3995.473                         mb/cnt/gclkms[1]
    SLICE_X33Y147        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/needrefresh_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X33Y147        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.117  3995.590 r  AG_dmac/AG_mbcnt     mb/cnt/needrefresh_reg/Q
                         net (fo=2, routed)           1.401  3996.991                         mb/cnt/needrefresh
    SLICE_X33Y147        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/needrefresha_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock mmcm_clkout0 rise edge)
                                                   3991.600  3991.600 r                       
    D23                                               0.000  3991.600 r                       cclkp (IN)
                         net (fo=0)                   0.001  3991.601                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352  3991.953 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051  3992.004                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000  3992.004 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649  3992.653                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075  3992.728 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096  3994.824                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335  3995.159 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.372  3995.531                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075  3995.606 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.796  3997.402                         mb/cnt/c0_ddr4_ui_clk
    SLICE_X33Y147        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/needrefresha_reg/C
                         clock pessimism              0.000  3997.402                           
                         clock uncertainty           -0.248  3997.154                           
    SLICE_X33Y147        FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.059  3997.213    AG_dmac/AG_mbcnt       mb/cnt/needrefresha_reg
  -------------------------------------------------------------------
                         required time                       3997.213                           
                         arrival time                       -3996.991                           
  -------------------------------------------------------------------
                         slack                                  0.221                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.072ns  (arrival time - required time)
  Source:                 mb/cnt/needrefresh_reg/C
                            (rising edge-triggered cell FDRE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mb/cnt/needrefresha_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - lclks rise@0.000ns)
  Data Path Delay:        1.195ns  (logic 0.106ns (8.870%)  route 1.089ns (91.130%))
  Logic Levels:           0  
  Clock Path Skew:        0.767ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.059ns
    Source Clock Delay      (SCD):    5.292ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.248ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.223ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      1.787ns (routing 0.683ns, distribution 1.104ns)
  Clock Net Delay (Destination): 2.027ns (routing 0.335ns, distribution 1.692ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock lclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     0.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     0.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     0.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     2.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                      0.335     3.058 r                       sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         0.372     3.430                         sc/lclks
    BUFGCE_X1Y51         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     3.505 r                       sc/_clkm/O
    X1Y2 (CLOCK_ROOT)    net (fo=13, routed)          1.787     5.292                         mb/cnt/gclkms[1]
    SLICE_X33Y147        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/needrefresh_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X33Y147        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.106     5.398 r  AG_dmac/AG_mbcnt     mb/cnt/needrefresh_reg/Q
                         net (fo=2, routed)           1.089     6.487                         mb/cnt/needrefresh
    SLICE_X33Y147        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/needrefresha_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     3.512 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        2.027     6.059                         mb/cnt/c0_ddr4_ui_clk
    SLICE_X33Y147        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/needrefresha_reg/C
                         clock pessimism              0.000     6.059                           
                         clock uncertainty            0.248     6.307                           
    SLICE_X33Y147        FDRE (Hold_AFF_SLICEL_C_D)
                                                      0.108     6.415    AG_dmac/AG_mbcnt       mb/cnt/needrefresha_reg
  -------------------------------------------------------------------
                         required time                         -6.415                           
                         arrival time                           6.487                           
  -------------------------------------------------------------------
                         slack                                  0.072                           





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[0]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.583ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.509ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.583ns  (required time - arrival time)
  Source:                 mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (pll_clk[0]_DIV rise@4.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.209ns  (logic 0.117ns (5.297%)  route 2.092ns (94.703%))
  Logic Levels:           0  
  Clock Path Skew:        -0.591ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.275ns = ( 9.275 - 4.000 ) 
    Source Clock Delay      (SCD):    5.918ns
    Clock Pessimism Removal (CPR):    0.052ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.071ns
    Phase Error              (PE):    0.131ns
  Clock Net Delay (Source):      1.886ns (routing 0.335ns, distribution 1.551ns)
  Clock Net Delay (Destination): 1.571ns (routing 0.309ns, distribution 1.262ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     3.512 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.886     5.918                         mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[6]
    SLICE_X1Y154         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X1Y154         FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.117     6.035 r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/Q
                         net (fo=8, routed)           2.092     8.127                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[2]
    BITSLICE_CONTROL_X0Y8
                         BITSLICE_CONTROL                             r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      4.000     4.000 r                       
    D23                                               0.000     4.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     4.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     4.352 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     4.403                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     4.403 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     5.052                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     5.127 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096     7.223                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     7.558 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.372     7.930                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     8.005 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.571     9.576                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLLE3_ADV_X0Y3       PLLE3_ADV (Prop_PLLE3_ADV_CLKIN_CLKOUTPHY)
                                                     -1.160     8.417 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.196     8.613                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y8
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_BIT_CTRL_OUT0[26])
                                                      0.662     9.275 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         clock pessimism              0.052     9.327                           
                         clock uncertainty           -0.181     9.146                           
    BITSLICE_CONTROL_X0Y8
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_BIT_CTRL_OUT0[26]_TBYTE_IN[2])
                                                     -0.436     8.710    AG_mb                  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          8.710                           
                         arrival time                          -8.127                           
  -------------------------------------------------------------------
                         slack                                  0.583                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.509ns  (arrival time - required time)
  Source:                 mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.477ns  (logic 0.104ns (21.803%)  route 0.373ns (78.197%))
  Logic Levels:           0  
  Clock Path Skew:        -0.289ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.425ns
    Source Clock Delay      (SCD):    5.662ns
    Clock Pessimism Removal (CPR):    0.052ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.071ns
    Phase Error              (PE):    0.131ns
  Clock Net Delay (Source):      1.656ns (routing 0.309ns, distribution 1.347ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     0.353 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     0.404                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.404 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     1.053                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     1.128 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096     3.224                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     3.559 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.372     3.931                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     4.006 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.656     5.662                         mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[6]_0
    SLICE_X0Y122         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[4]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X0Y122         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.104     5.766 r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[4]/Q
                         net (fo=1, routed)           0.373     6.139                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[4]
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE                                r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f                       
    D23                                               0.000     0.000 f                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     3.512 f  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 f  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=9656, routed)        1.734     5.766                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLLE3_ADV_X0Y3       PLLE3_ADV (Prop_PLLE3_ADV_CLKIN_CLKOUTPHY)
                                                     -1.391     4.375 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.235     4.610                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_BIT_CTRL_OUT2[26])
                                                      0.803     5.413 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.012     5.425                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE                                r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.052     5.373                           
                         clock uncertainty            0.181     5.554                           
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                      0.076     5.630    AG_mb                  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -5.630                           
                         arrival time                           6.139                           
  -------------------------------------------------------------------
                         slack                                  0.509                           





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[1]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        1.372ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.463ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.372ns  (required time - arrival time)
  Source:                 mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (pll_clk[1]_DIV rise@4.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.304ns  (logic 0.114ns (8.742%)  route 1.190ns (91.258%))
  Logic Levels:           0  
  Clock Path Skew:        -0.552ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.278ns = ( 9.278 - 4.000 ) 
    Source Clock Delay      (SCD):    5.934ns
    Clock Pessimism Removal (CPR):    0.104ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.071ns
    Phase Error              (PE):    0.131ns
  Clock Net Delay (Source):      1.902ns (routing 0.335ns, distribution 1.567ns)
  Clock Net Delay (Destination): 1.574ns (routing 0.309ns, distribution 1.265ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     3.512 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.902     5.934                         mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X8Y152         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X8Y152         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.114     6.048 r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           1.190     7.238                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y18
                         BITSLICE_CONTROL                             r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      4.000     4.000 f                       
    D23                                               0.000     4.000 f                       cclkp (IN)
                         net (fo=0)                   0.001     4.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     4.352 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     4.403                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     4.403 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     5.052                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     5.127 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096     7.223                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     7.558 f  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.372     7.930                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     8.005 f  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.574     9.579                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLLE3_ADV_X0Y5       PLLE3_ADV (Prop_PLLE3_ADV_CLKIN_CLKOUTPHY)
                                                     -1.160     8.420 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.196     8.616                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y18
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_BIT_CTRL_OUT0[26])
                                                      0.662     9.278 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         clock pessimism              0.104     9.382                           
                         clock uncertainty           -0.181     9.201                           
    BITSLICE_CONTROL_X0Y18
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_BIT_CTRL_OUT0[26]_PHY_RDEN[2])
                                                     -0.591     8.610    AG_mb                  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          8.610                           
                         arrival time                          -7.238                           
  -------------------------------------------------------------------
                         slack                                  1.372                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.463ns  (arrival time - required time)
  Source:                 mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.389ns  (logic 0.104ns (26.735%)  route 0.285ns (73.265%))
  Logic Levels:           0  
  Clock Path Skew:        -0.337ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.425ns
    Source Clock Delay      (SCD):    5.660ns
    Clock Pessimism Removal (CPR):    0.103ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.071ns
    Phase Error              (PE):    0.131ns
  Clock Net Delay (Source):      1.654ns (routing 0.309ns, distribution 1.345ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     0.353 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     0.404                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.404 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     1.053                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     1.128 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096     3.224                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     3.559 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.372     3.931                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     4.006 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.654     5.660                         mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[6]_0
    SLICE_X0Y132         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[2]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X0Y132         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.104     5.764 r  AG_mb                mb/mig/inst/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[2]/Q
                         net (fo=1, routed)           0.285     6.049                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[2]
    BITSLICE_RX_TX_X0Y114
                         RXTX_BITSLICE                                r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f                       
    D23                                               0.000     0.000 f                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     3.512 f  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 f  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=9656, routed)        1.740     5.772                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLLE3_ADV_X0Y5       PLLE3_ADV (Prop_PLLE3_ADV_CLKIN_CLKOUTPHY)
                                                     -1.391     4.381 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.235     4.616                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y17
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_BIT_CTRL_OUT4[26])
                                                      0.797     5.413 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.012     5.425                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y114
                         RXTX_BITSLICE                                r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.103     5.323                           
                         clock uncertainty            0.181     5.503                           
    BITSLICE_RX_TX_X0Y114
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                      0.082     5.585    AG_mb                  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -5.585                           
                         arrival time                           6.049                           
  -------------------------------------------------------------------
                         slack                                  0.463                           





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[2]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        1.006ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.486ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.006ns  (required time - arrival time)
  Source:                 mb/mig/inst/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (pll_clk[2]_DIV rise@4.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.817ns  (logic 0.116ns (6.384%)  route 1.701ns (93.616%))
  Logic Levels:           0  
  Clock Path Skew:        -0.564ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.320ns = ( 9.320 - 4.000 ) 
    Source Clock Delay      (SCD):    5.991ns
    Clock Pessimism Removal (CPR):    0.107ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.071ns
    Phase Error              (PE):    0.131ns
  Clock Net Delay (Source):      1.959ns (routing 0.335ns, distribution 1.624ns)
  Clock Net Delay (Destination): 1.616ns (routing 0.309ns, distribution 1.307ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     3.512 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.959     5.991                         mb/mig/inst/u_mig_ddr4_phy/inst/div_clk
    SLICE_X13Y185        FDRE                                         r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[1]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X13Y185        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.116     6.107 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[1]/Q
                         net (fo=5, routed)           1.701     7.808                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[1]
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL                             r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      4.000     4.000 f                       
    D23                                               0.000     4.000 f                       cclkp (IN)
                         net (fo=0)                   0.001     4.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     4.352 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     4.403                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     4.403 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     5.052                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     5.127 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096     7.223                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     7.558 f  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.372     7.930                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     8.005 f  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.616     9.621                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLLE3_ADV_X0Y7       PLLE3_ADV (Prop_PLLE3_ADV_CLKIN_CLKOUTPHY)
                                                     -1.160     8.462 f  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=5, routed)           0.196     8.658                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_BIT_CTRL_OUT0[26])
                                                      0.662     9.320 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         clock pessimism              0.107     9.427                           
                         clock uncertainty           -0.181     9.246                           
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_BIT_CTRL_OUT0[26]_TBYTE_IN[1])
                                                     -0.432     8.814    AG_mb                  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          8.814                           
                         arrival time                          -7.808                           
  -------------------------------------------------------------------
                         slack                                  1.006                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.486ns  (arrival time - required time)
  Source:                 mb/mig/inst/u_ddr_cal_top/mcal_ADR_dly_reg[0][16]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.453ns  (logic 0.107ns (23.620%)  route 0.346ns (76.380%))
  Logic Levels:           0  
  Clock Path Skew:        -0.259ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.446ns
    Source Clock Delay      (SCD):    5.653ns
    Clock Pessimism Removal (CPR):    0.052ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.071ns
    Phase Error              (PE):    0.131ns
  Clock Net Delay (Source):      1.647ns (routing 0.309ns, distribution 1.338ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     0.353 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     0.404                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.404 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     1.053                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     1.128 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096     3.224                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     3.559 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.372     3.931                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     4.006 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.647     5.653                         mb/mig/inst/u_ddr_cal_top/dReg_reg[6]
    SLICE_X0Y179         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/mcal_ADR_dly_reg[0][16]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X0Y179         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.107     5.760 r  AG_mb                mb/mig/inst/u_ddr_cal_top/mcal_ADR_dly_reg[0][16]/Q
                         net (fo=1, routed)           0.346     6.106                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[0]
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE                                r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     3.512 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=9656, routed)        1.785     5.817                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLLE3_ADV_X0Y7       PLLE3_ADV (Prop_PLLE3_ADV_CLKIN_CLKOUTPHY)
                                                     -1.391     4.426 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=5, routed)           0.235     4.661                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_BIT_CTRL_OUT0[26])
                                                      0.773     5.434 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.012     5.446                         mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE                                r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.052     5.394                           
                         clock uncertainty            0.181     5.575                           
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.045     5.620    AG_mb                  mb/mig/inst/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -5.620                           
                         arrival time                           6.106                           
  -------------------------------------------------------------------
                         slack                                  0.486                           





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        2.552ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.053ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.552ns  (required time - arrival time)
  Source:                 mb/mig/inst/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/mig/inst/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@4.000ns period=7.999ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (mmcm_clkout6 rise@7.999ns - mmcm_clkout0 rise@4.000ns)
  Data Path Delay:        1.032ns  (logic 0.114ns (11.047%)  route 0.918ns (88.953%))
  Logic Levels:           0  
  Clock Path Skew:        -0.284ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.685ns = ( 13.684 - 7.999 ) 
    Source Clock Delay      (SCD):    5.922ns = ( 9.922 - 4.000 ) 
    Clock Pessimism Removal (CPR):    -0.047ns
  Clock Uncertainty:      0.191ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.890ns (routing 0.335ns, distribution 1.555ns)
  Clock Net Delay (Destination): 1.679ns (routing 0.309ns, distribution 1.370ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      4.000     4.000 r                       
    D23                                               0.000     4.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     4.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     4.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     4.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     4.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     5.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     5.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     7.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     7.512 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     7.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     8.032 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        1.890     9.922                         mb/mig/inst/u_ddr_cal_top/dReg_reg[6]
    SLICE_X3Y163         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X3Y163         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.114    10.036 r  AG_mb                mb/mig/inst/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           0.918    10.954                         mb/mig/inst/u_ddr_cal_riu/sample_gts
    SLICE_X8Y159         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock mmcm_clkout6 rise edge)
                                                      7.999     7.999 r                       
    D23                                               0.000     7.999 r                       cclkp (IN)
                         net (fo=0)                   0.001     8.000                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.352     8.352 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.051     8.403                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     8.403 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.649     9.052                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     9.127 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.096    11.223                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT6)
                                                      0.335    11.558 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.372    11.930                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y57         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075    12.005 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=1742, routed)        1.679    13.684                         mb/mig/inst/u_ddr_cal_riu/CLK
    SLICE_X8Y159         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism             -0.047    13.637                           
                         clock uncertainty           -0.191    13.446                           
    SLICE_X8Y159         FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.060    13.506    AG_mb                  mb/mig/inst/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                         13.506                           
                         arrival time                         -10.954                           
  -------------------------------------------------------------------
                         slack                                  2.552                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.053ns  (arrival time - required time)
  Source:                 mb/mig/inst/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/mig/inst/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@4.000ns period=7.999ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.505ns  (logic 0.049ns (9.703%)  route 0.456ns (90.297%))
  Logic Levels:           0  
  Clock Path Skew:        0.205ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.985ns
    Source Clock Delay      (SCD):    2.842ns
    Clock Pessimism Removal (CPR):    -0.062ns
  Clock Uncertainty:      0.191ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.762ns (routing 0.127ns, distribution 0.635ns)
  Clock Net Delay (Destination): 0.921ns (routing 0.142ns, distribution 0.779ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.213     0.214 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.028     0.242                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.242 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.350     0.592                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     0.619 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.997     1.616                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.886 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.167     2.053                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     2.080 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        0.762     2.842                         mb/mig/inst/u_ddr_cal_top/dReg_reg[6]
    SLICE_X3Y163         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X3Y163         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.049     2.891 r  AG_mb                mb/mig/inst/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           0.456     3.347                         mb/mig/inst/u_ddr_cal_riu/sample_gts
    SLICE_X8Y159         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.396     0.397 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.048     0.445                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.445 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.409     0.854                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     0.885 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.146     2.031                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT6)
                                                     -0.207     1.824 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.209     2.033                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y57         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     2.064 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=1742, routed)        0.921     2.985                         mb/mig/inst/u_ddr_cal_riu/CLK
    SLICE_X8Y159         FDRE                                         r  AG_mb                mb/mig/inst/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism              0.062     3.047                           
                         clock uncertainty            0.191     3.238                           
    SLICE_X8Y159         FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.056     3.294    AG_mb                  mb/mig/inst/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                         -3.294                           
                         arrival time                           3.347                           
  -------------------------------------------------------------------
                         slack                                  0.053                           





---------------------------------------------------------------------------------------------------
From Clock:  lclks
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK

Setup :            0  Failing Endpoints,  Worst Slack        9.266ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             9.266ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {rise@0.000ns fall@16.500ns period=33.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (MaxDelay Path 10.000ns)
  Data Path Delay:        0.796ns  (logic 0.114ns (14.322%)  route 0.682ns (85.678%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 10.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y159                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X33Y159        FDCE (Prop_FFF_SLICEL_C_Q)
                                                      0.114     0.114 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.682     0.796    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X33Y159        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   10.000    10.000    
    SLICE_X33Y159        FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.062    10.062    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         10.062    
                         arrival time                          -0.796    
  -------------------------------------------------------------------
                         slack                                  9.266    





---------------------------------------------------------------------------------------------------
From Clock:  drck2
  To Clock:  genblk1[0].user_clk_1

Setup :            0  Failing Endpoints,  Worst Slack        0.985ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.943ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.985ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].prc/cdatad_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by drck2  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            nvmp/genblk1[0].prc/code_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             genblk1[0].user_clk_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (genblk1[0].user_clk_1 rise@4.000ns - drck2 rise@0.000ns)
  Data Path Delay:        0.573ns  (logic 0.116ns (20.244%)  route 0.457ns (79.756%))
  Logic Levels:           0  
  Clock Path Skew:        -2.469ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.998ns = ( 5.998 - 4.000 ) 
    Source Clock Delay      (SCD):    4.467ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.249ns (routing 0.335ns, distribution 1.914ns)
  Clock Net Delay (Destination): 1.669ns (routing 0.548ns, distribution 1.121ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock drck2 rise edge)      0.000     0.000 r                       
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r                       bsif/bs/DRCK
                         net (fo=1, routed)           2.135     2.135                         bsif/drck2
    BUFGCE_X1Y52         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     2.218 r                       bsif/_clk/O
    X2Y2 (CLOCK_ROOT)    net (fo=255, routed)         2.249     4.467                         nvmp/genblk1[0].prc/CLK
    SLICE_X92Y110        FDRE                                         r  AG_nvmprc            nvmp/genblk1[0].prc/cdatad_reg[7]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X92Y110        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.116     4.583 r  AG_nvmprc            nvmp/genblk1[0].prc/cdatad_reg[7]/Q
                         net (fo=3, routed)           0.457     5.040                         nvmp/genblk1[0].prc/p_1_in[7]
    SLICE_X92Y110        FDRE                                         r  AG_nvmprc            nvmp/genblk1[0].prc/code_reg[7]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock genblk1[0].user_clk_1 rise edge)
                                                      4.000     4.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     4.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.046     4.046                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.329 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.669     5.998                         nvmp/genblk1[0].prc/CLK_USERCLK
    SLICE_X92Y110        FDRE                                         r  AG_nvmprc            nvmp/genblk1[0].prc/code_reg[7]/C
                         clock pessimism              0.000     5.998                           
                         clock uncertainty           -0.035     5.963                           
    SLICE_X92Y110        FDRE (Setup_BFF2_SLICEL_C_D)
                                                      0.062     6.025    AG_nvmprc              nvmp/genblk1[0].prc/code_reg[7]
  -------------------------------------------------------------------
                         required time                          6.025                           
                         arrival time                          -5.040                           
  -------------------------------------------------------------------
                         slack                                  0.985                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.943ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].prc/cdatad_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by drck2  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            nvmp/genblk1[0].prc/code_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             genblk1[0].user_clk_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (genblk1[0].user_clk_1 rise@0.000ns - drck2 rise@0.000ns)
  Data Path Delay:        0.183ns  (logic 0.048ns (26.229%)  route 0.135ns (73.770%))
  Logic Levels:           0  
  Clock Path Skew:        -0.851ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.187ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.990ns (routing 0.127ns, distribution 0.863ns)
  Clock Net Delay (Destination): 1.022ns (routing 0.348ns, distribution 0.674ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock drck2 rise edge)      0.000     0.000 r                       
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r                       bsif/bs/DRCK
                         net (fo=1, routed)           1.021     1.021                         bsif/drck2
    BUFGCE_X1Y52         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.048 r                       bsif/_clk/O
    X2Y2 (CLOCK_ROOT)    net (fo=255, routed)         0.990     2.038                         nvmp/genblk1[0].prc/CLK
    SLICE_X92Y111        FDRE                                         r  AG_nvmprc            nvmp/genblk1[0].prc/cdatad_reg[1]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X92Y111        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.048     2.086 r  AG_nvmprc            nvmp/genblk1[0].prc/cdatad_reg[1]/Q
                         net (fo=3, routed)           0.135     2.221                         nvmp/genblk1[0].prc/p_1_in[1]
    SLICE_X91Y109        FDRE                                         r  AG_nvmprc            nvmp/genblk1[0].prc/code_reg[1]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.035     0.035                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.022     1.187                         nvmp/genblk1[0].prc/CLK_USERCLK
    SLICE_X91Y109        FDRE                                         r  AG_nvmprc            nvmp/genblk1[0].prc/code_reg[1]/C
                         clock pessimism              0.000     1.187                           
                         clock uncertainty            0.035     1.222                           
    SLICE_X91Y109        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.056     1.278    AG_nvmprc              nvmp/genblk1[0].prc/code_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.278                           
                         arrival time                           2.221                           
  -------------------------------------------------------------------
                         slack                                  0.943                           





---------------------------------------------------------------------------------------------------
From Clock:  gclkx
  To Clock:  genblk1[0].user_clk_1

Setup :            0  Failing Endpoints,  Worst Slack        0.285ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.553ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.285ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].xiow/vfa/virdy_reg/C
                            (rising edge-triggered cell FDCE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            nvmp/genblk1[0].prc/j1/mstkx/m/outr_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             genblk1[0].user_clk_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.973ns  (logic 0.310ns (31.860%)  route 0.663ns (68.140%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        -3.654ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.002ns
    Source Clock Delay      (SCD):    5.656ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.190ns (routing 0.335ns, distribution 1.855ns)
  Clock Net Delay (Destination): 1.673ns (routing 0.548ns, distribution 1.125ns)
  Timing Exception:       MaxDelay Path 5.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.190     5.656                         nvmp/genblk1[0].xiow/vfa/ioclk
    SLICE_X87Y97         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].xiow/vfa/virdy_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X87Y97         FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     5.770 r  AG_nvmp              nvmp/genblk1[0].xiow/vfa/virdy_reg/Q
                         net (fo=3, routed)           0.071     5.841                         nvmp/genblk1[0].prc/j1/mstkx/m/virdy[0]
    SLICE_X87Y97         LUT4 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.116     5.957 r  AG_nvmprc            nvmp/genblk1[0].prc/j1/mstkx/m/outr[16]_i_4/O
                         net (fo=1, routed)           0.426     6.383                         nvmp/genblk1[0].prc/j1/ncr1.code/dpw[0].sdr.inst/outr_reg[16]
    SLICE_X88Y102        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.040     6.423 r  AG_nvmprc            nvmp/genblk1[0].prc/j1/ncr1.code/dpw[0].sdr.inst/outr[16]_i_2/O
                         net (fo=1, routed)           0.143     6.566                         nvmp/genblk1[0].prc/j1/ncr1.code/dpw[0].sdr.inst/outr[16]_i_2_n_0
    SLICE_X88Y101        LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.040     6.606 r  AG_nvmprc            nvmp/genblk1[0].prc/j1/ncr1.code/dpw[0].sdr.inst/outr[16]_i_1__0/O
                         net (fo=1, routed)           0.023     6.629                         nvmp/genblk1[0].prc/j1/mstkx/m/outp[16]
    SLICE_X88Y101        FDRE                                         r  AG_nvmprc            nvmp/genblk1[0].prc/j1/mstkx/m/outr_reg[16]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    5.000     5.000                         
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     5.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.046     5.046                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     5.329 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.673     7.002                         nvmp/genblk1[0].prc/j1/mstkx/m/CLK_USERCLK
    SLICE_X88Y101        FDRE                                         r  AG_nvmprc            nvmp/genblk1[0].prc/j1/mstkx/m/outr_reg[16]/C
                         clock pessimism              0.000     7.002                           
                         clock uncertainty           -0.147     6.855                           
    SLICE_X88Y101        FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.059     6.914    AG_nvmprc              nvmp/genblk1[0].prc/j1/mstkx/m/outr_reg[16]
  -------------------------------------------------------------------
                         required time                          6.914                           
                         arrival time                          -6.629                           
  -------------------------------------------------------------------
                         slack                                  0.285                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.553ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].xiow/vfa/vcnt_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            nvmp/genblk1[0].xiow/wfa/wtop_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             genblk1[0].user_clk_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (genblk1[0].user_clk_1 rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.147ns  (logic 0.048ns (32.653%)  route 0.099ns (67.347%))
  Logic Levels:           0  
  Clock Path Skew:        -1.608ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.204ns
    Source Clock Delay      (SCD):    2.812ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.959ns (routing 0.127ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.039ns (routing 0.348ns, distribution 0.691ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.959     2.812                         nvmp/genblk1[0].xiow/vfa/ioclk
    SLICE_X86Y65         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].xiow/vfa/vcnt_reg[5]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X86Y65         FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.048     2.860 r  AG_nvmp              nvmp/genblk1[0].xiow/vfa/vcnt_reg[5]/Q
                         net (fo=10, routed)          0.099     2.959                         nvmp/genblk1[0].xiow/wfa/D[2]
    SLICE_X86Y63         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].xiow/wfa/wtop_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.035     0.035                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.039     1.204                         nvmp/genblk1[0].xiow/wfa/CLK_USERCLK
    SLICE_X86Y63         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].xiow/wfa/wtop_reg[2]/C
                         clock pessimism              0.000     1.204                           
                         clock uncertainty            0.147     1.351                           
    SLICE_X86Y63         FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.055     1.406    AG_nvmp                nvmp/genblk1[0].xiow/wfa/wtop_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.406                           
                         arrival time                           2.959                           
  -------------------------------------------------------------------
                         slack                                  1.553                           





---------------------------------------------------------------------------------------------------
From Clock:  GTHE3_CHANNEL_RXOUTCLK[0]
  To Clock:  genblk1[0].user_clk_1

Setup :            0  Failing Endpoints,  Worst Slack        2.899ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.037ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.899ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].cf0/vcnt_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            nvmp/genblk1[0].prc/j1/mstkx/m/outr_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             genblk1[0].user_clk_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        1.497ns  (logic 0.400ns (26.720%)  route 1.097ns (73.280%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        -0.628ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.998ns
    Source Clock Delay      (SCD):    2.626ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.229ns (routing 0.702ns, distribution 1.527ns)
  Clock Net Delay (Destination): 1.669ns (routing 0.548ns, distribution 1.121ns)
  Timing Exception:       MaxDelay Path 5.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        2.229     2.626                         nvmp/genblk1[0].cf0/rclk1[0]
    SLICE_X86Y101        FDRE                                         r  AG_nvmp              nvmp/genblk1[0].cf0/vcnt_reg[5]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X86Y101        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.113     2.739 r  AG_nvmp              nvmp/genblk1[0].cf0/vcnt_reg[5]/Q
                         net (fo=5, routed)           0.553     3.292                         nvmp/genblk1[0].prc/j1/mstkx/m/genblk1[0].rcstat[1]
    SLICE_X90Y100        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.040     3.332 r  AG_nvmprc            nvmp/genblk1[0].prc/j1/mstkx/m/outr[21]_i_3/O
                         net (fo=1, routed)           0.287     3.619                         nvmp/genblk1[0].prc/j1/ncr1.code/dpw[0].sdr.inst/genblk1[0].srdbusx[8]
    SLICE_X89Y99         LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.132     3.751 r  AG_nvmprc            nvmp/genblk1[0].prc/j1/ncr1.code/dpw[0].sdr.inst/outr[21]_i_2/O
                         net (fo=1, routed)           0.230     3.981                         nvmp/genblk1[0].prc/j1/ncr1.code/dpw[0].sdr.inst/outr[21]_i_2_n_0
    SLICE_X89Y104        LUT5 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.115     4.096 r  AG_nvmprc            nvmp/genblk1[0].prc/j1/ncr1.code/dpw[0].sdr.inst/outr[21]_i_1__0/O
                         net (fo=1, routed)           0.027     4.123                         nvmp/genblk1[0].prc/j1/mstkx/m/outp[21]
    SLICE_X89Y104        FDRE                                         r  AG_nvmprc            nvmp/genblk1[0].prc/j1/mstkx/m/outr_reg[21]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    5.000     5.000                         
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     5.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.046     5.046                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     5.329 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.669     6.998                         nvmp/genblk1[0].prc/j1/mstkx/m/CLK_USERCLK
    SLICE_X89Y104        FDRE                                         r  AG_nvmprc            nvmp/genblk1[0].prc/j1/mstkx/m/outr_reg[21]/C
                         clock pessimism              0.000     6.998                           
                         clock uncertainty           -0.035     6.963                           
    SLICE_X89Y104        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.059     7.022    AG_nvmprc              nvmp/genblk1[0].prc/j1/mstkx/m/outr_reg[21]
  -------------------------------------------------------------------
                         required time                          7.022                           
                         arrival time                          -4.123                           
  -------------------------------------------------------------------
                         slack                                  2.899                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].cf0/vcnt_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            nvmp/genblk1[0].cf0/vcntx_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             genblk1[0].user_clk_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (genblk1[0].user_clk_1 rise@0.000ns - GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        0.193ns  (logic 0.049ns (25.389%)  route 0.144ns (74.611%))
  Logic Levels:           0  
  Clock Path Skew:        0.065ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.185ns
    Source Clock Delay      (SCD):    1.120ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.002ns (routing 0.371ns, distribution 0.631ns)
  Clock Net Delay (Destination): 1.020ns (routing 0.348ns, distribution 0.672ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.002     1.120                         nvmp/genblk1[0].cf0/rclk1[0]
    SLICE_X86Y101        FDRE                                         r  AG_nvmp              nvmp/genblk1[0].cf0/vcnt_reg[3]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X86Y101        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.049     1.169 r  AG_nvmp              nvmp/genblk1[0].cf0/vcnt_reg[3]/Q
                         net (fo=7, routed)           0.144     1.313                         nvmp/genblk1[0].cf0/genblk1[0].rcstat[12]
    SLICE_X87Y103        FDRE                                         r  AG_nvmp              nvmp/genblk1[0].cf0/vcntx_reg[3]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.035     0.035                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.020     1.185                         nvmp/genblk1[0].cf0/user_clk
    SLICE_X87Y103        FDRE                                         r  AG_nvmp              nvmp/genblk1[0].cf0/vcntx_reg[3]/C
                         clock pessimism              0.000     1.185                           
                         clock uncertainty            0.035     1.220                           
    SLICE_X87Y103        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.056     1.276    AG_nvmp                nvmp/genblk1[0].cf0/vcntx_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.276                           
                         arrival time                           1.313                           
  -------------------------------------------------------------------
                         slack                                  0.037                           





---------------------------------------------------------------------------------------------------
From Clock:  genblk1[0].user_clk_1
  To Clock:  pipe_clk_1

Setup :            0  Failing Endpoints,  Worst Slack        0.887ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.112ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.887ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/pipe_stages_1.pipe_tx_eqcontrol_q_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by pipe_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             pipe_clk_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (pipe_clk_1 rise@4.000ns - genblk1[0].user_clk_1 rise@0.000ns)
  Data Path Delay:        2.766ns  (logic 0.234ns (8.460%)  route 2.532ns (91.540%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.229ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.030ns = ( 6.030 - 4.000 ) 
    Source Clock Delay      (SCD):    2.271ns
    Clock Pessimism Removal (CPR):    0.012ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.874ns (routing 0.606ns, distribution 1.268ns)
  Clock Net Delay (Destination): 1.701ns (routing 0.563ns, distribution 1.138ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.082     0.082                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.874     2.271                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/CLK_USERCLK
    SLICE_X94Y52         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[2]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X94Y52         FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.114     2.385 f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[2]/Q
                         net (fo=6, routed)           0.088     2.473                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg_n_0_[2]
    SLICE_X94Y52         LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.120     2.593 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/pipe_stages_1.pipe_tx_eqcontrol_q[1]_i_1/O
                         net (fo=505, routed)         2.444     5.037                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/pipe_stages_1.pipe_tx_eqcoeff_q_reg[0]_0
    SLICE_X86Y5          FDRE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/pipe_stages_1.pipe_tx_eqcontrol_q_reg[1]/R
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pipe_clk_1 rise edge)
                                                      4.000     4.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     4.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.046     4.046                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y43        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.329 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_pclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=1126, routed)        1.701     6.030                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/CLK_PCLK
    SLICE_X86Y5          FDRE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/pipe_stages_1.pipe_tx_eqcontrol_q_reg[1]/C
                         clock pessimism              0.012     6.042                           
                         clock uncertainty           -0.035     6.007                           
    SLICE_X86Y5          FDRE (Setup_EFF_SLICEL_C_R)
                                                     -0.083     5.924    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/pipe_stages_1.pipe_tx_eqcontrol_q_reg[1]
  -------------------------------------------------------------------
                         required time                          5.924                           
                         arrival time                          -5.037                           
  -------------------------------------------------------------------
                         slack                                  0.887                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.112ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/pipe_stages_1.pipe_tx_data_q_reg[23]/R
                            (rising edge-triggered cell FDRE clocked by pipe_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             pipe_clk_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (pipe_clk_1 rise@0.000ns - genblk1[0].user_clk_1 rise@0.000ns)
  Data Path Delay:        0.325ns  (logic 0.080ns (24.615%)  route 0.245ns (75.385%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.208ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.158ns
    Source Clock Delay      (SCD):    0.945ns
    Clock Pessimism Removal (CPR):    0.005ns
  Clock Net Delay (Source):      0.827ns (routing 0.306ns, distribution 0.521ns)
  Clock Net Delay (Destination): 0.993ns (routing 0.360ns, distribution 0.633ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.018     0.018                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         0.827     0.945                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/CLK_USERCLK
    SLICE_X94Y52         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[0]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X94Y52         FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.048     0.993 f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[0]/Q
                         net (fo=6, routed)           0.041     1.034                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg_n_0_[0]
    SLICE_X94Y52         LUT2 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.032     1.066 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/pipe_stages_1.pipe_tx_eqcontrol_q[1]_i_1/O
                         net (fo=505, routed)         0.204     1.270                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/pipe_stages_1.pipe_tx_eqcoeff_q_reg[0]_0
    SLICE_X95Y51         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/pipe_stages_1.pipe_tx_data_q_reg[23]/R
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pipe_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.035     0.035                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y43        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_pclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=1126, routed)        0.993     1.158                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/CLK_PCLK
    SLICE_X95Y51         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/pipe_stages_1.pipe_tx_data_q_reg[23]/C
                         clock pessimism             -0.005     1.153                           
    SLICE_X95Y51         FDRE (Hold_EFF_SLICEL_C_R)
                                                      0.005     1.158    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/pipe_pipeline_inst/pipe_4_lane.pipe_lane_3_inst/pipe_stages_1.pipe_tx_data_q_reg[23]
  -------------------------------------------------------------------
                         required time                         -1.158                           
                         arrival time                           1.270                           
  -------------------------------------------------------------------
                         slack                                  0.112                           





---------------------------------------------------------------------------------------------------
From Clock:  gclkx
  To Clock:  gclkf

Setup :            0  Failing Endpoints,  Worst Slack        3.812ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.037ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.812ns  (required time - arrival time)
  Source:                 ppc/sadx_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            sbx/sadf_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             gclkf
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.894ns  (logic 0.118ns (4.077%)  route 2.776ns (95.923%))
  Logic Levels:           0  
  Clock Path Skew:        0.890ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.100ns
    Source Clock Delay      (SCD):    5.521ns
    Clock Pessimism Removal (CPR):    0.311ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.214ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      2.055ns (routing 0.335ns, distribution 1.720ns)
  Clock Net Delay (Destination): 2.657ns (routing 0.991ns, distribution 1.666ns)
  Timing Exception:       MaxDelay Path 6.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.055     5.521                         ppc/ioclk
    SLICE_X53Y148        FDRE                                         r  AG_dmac/AG_ppc       ppc/sadx_reg[15]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X53Y148        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.118     5.639 r  AG_dmac/AG_ppc       ppc/sadx_reg[15]/Q
                         net (fo=5, routed)           2.776     8.415                         sbx/sads_reg[31]_0[15]
    SLICE_X53Y149        FDRE                                         r  AG_dmac/AG_ppc/AG_sbx
                                                                                              sbx/sadf_reg[15]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    6.000     6.000                         
    GTHE3_COMMON_X0Y2                                 0.000     6.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     6.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     6.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     6.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.128     8.687                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     9.022 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.346     9.368                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     9.443 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      2.657    12.100                         sbx/CLK
    SLICE_X53Y149        FDRE                                         r  AG_dmac/AG_ppc/AG_sbx
                                                                                              sbx/sadf_reg[15]/C
                         clock pessimism              0.311    12.411                           
                         clock uncertainty           -0.244    12.167                           
    SLICE_X53Y149        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.060    12.227    AG_dmac/AG_ppc/AG_sbx
                                                                                                sbx/sadf_reg[15]
  -------------------------------------------------------------------
                         required time                         12.227                           
                         arrival time                          -8.415                           
  -------------------------------------------------------------------
                         slack                                  3.812                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 core1/cor[4].p1.engi/rfp/f_o/wfa/vcnt_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            core1/cor[4].p1.engi/rfp/f_o/vfa/wtop_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             gclkf
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclkf rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.470ns  (logic 0.048ns (10.213%)  route 0.422ns (89.787%))
  Logic Levels:           0  
  Clock Path Skew:        0.134ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.091ns
    Source Clock Delay      (SCD):    2.760ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.214ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      0.907ns (routing 0.127ns, distribution 0.780ns)
  Clock Net Delay (Destination): 1.377ns (routing 0.583ns, distribution 0.794ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.907     2.760                         core1/cor[4].p1.engi/rfp/f_o/wfa/ioclk
    SLICE_X29Y141        FDCE                                         r  AG_cores             core1/cor[4].p1.engi/rfp/f_o/wfa/vcnt_reg[8]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X29Y141        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.048     2.808 r  AG_cores             core1/cor[4].p1.engi/rfp/f_o/wfa/vcnt_reg[8]/Q
                         net (fo=7, routed)           0.422     3.230                         core1/cor[4].p1.engi/rfp/f_o/vfa/wtop_reg[3]_0[2]
    SLICE_X34Y121        FDRE                                         r  AG_cores             core1/cor[4].p1.engi/rfp/f_o/vfa/wtop_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.244     1.681                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.207     1.474 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.209     1.683                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.714 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      1.377     3.091                         core1/cor[4].p1.engi/rfp/f_o/vfa/gclkf[0]
    SLICE_X34Y121        FDRE                                         r  AG_cores             core1/cor[4].p1.engi/rfp/f_o/vfa/wtop_reg[2]/C
                         clock pessimism             -0.197     2.894                           
                         clock uncertainty            0.244     3.139                           
    SLICE_X34Y121        FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.055     3.194    AG_cores               core1/cor[4].p1.engi/rfp/f_o/vfa/wtop_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.194                           
                         arrival time                           3.230                           
  -------------------------------------------------------------------
                         slack                                  0.037                           





---------------------------------------------------------------------------------------------------
From Clock:  gclky
  To Clock:  gclkf

Setup :            0  Failing Endpoints,  Worst Slack        0.561ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.037ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.561ns  (required time - arrival time)
  Source:                 ppc/j1/swrbus_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            sbx/swrbusf_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             gclkf
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.000ns  (MaxDelay Path 2.000ns)
  Data Path Delay:        2.830ns  (logic 0.115ns (4.064%)  route 2.715ns (95.936%))
  Logic Levels:           0  
  Clock Path Skew:        1.577ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.129ns
    Source Clock Delay      (SCD):    4.863ns
    Clock Pessimism Removal (CPR):    0.311ns
  Clock Uncertainty:      0.246ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.217ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      1.228ns (routing 0.009ns, distribution 1.219ns)
  Clock Net Delay (Destination): 2.686ns (routing 0.991ns, distribution 1.695ns)
  Timing Exception:       MaxDelay Path 2.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.228     4.863                         ppc/j1/bclk
    SLICE_X56Y143        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/swrbus_reg[0]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X56Y143        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.115     4.978 r  AG_dmac/AG_ppc       ppc/j1/swrbus_reg[0]/Q
                         net (fo=10, routed)          2.715     7.693                         sbx/D[0]
    SLICE_X57Y156        FDRE                                         r  AG_dmac/AG_ppc/AG_sbx
                                                                                              sbx/swrbusf_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    2.000     2.000                         
    GTHE3_COMMON_X0Y2                                 0.000     2.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     2.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     2.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     2.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     2.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.128     4.687                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     5.022 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.346     5.368                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     5.443 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      2.686     8.129                         sbx/CLK
    SLICE_X57Y156        FDRE                                         r  AG_dmac/AG_ppc/AG_sbx
                                                                                              sbx/swrbusf_reg[0]/C
                         clock pessimism              0.311     8.440                           
                         clock uncertainty           -0.246     8.194                           
    SLICE_X57Y156        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.060     8.254    AG_dmac/AG_ppc/AG_sbx
                                                                                                sbx/swrbusf_reg[0]
  -------------------------------------------------------------------
                         required time                          8.254                           
                         arrival time                          -7.693                           
  -------------------------------------------------------------------
                         slack                                  0.561                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 ppc/j1/swrbus_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            sbx/swrbusf_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             gclkf
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (gclkf rise@0.000ns - gclky rise@0.000ns)
  Data Path Delay:        1.768ns  (logic 0.103ns (5.826%)  route 1.665ns (94.174%))
  Logic Levels:           0  
  Clock Path Skew:        1.378ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.397ns
    Source Clock Delay      (SCD):    4.708ns
    Clock Pessimism Removal (CPR):    0.311ns
  Clock Uncertainty:      0.246ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.217ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      1.070ns (routing 0.009ns, distribution 1.061ns)
  Clock Net Delay (Destination): 3.004ns (routing 1.079ns, distribution 1.925ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     0.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     0.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     0.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     2.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335     3.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356     3.414                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224     3.638 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.070     4.708                         ppc/j1/bclk
    SLICE_X55Y150        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/swrbus_reg[12]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X55Y150        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.103     4.811 r  AG_dmac/AG_ppc       ppc/j1/swrbus_reg[12]/Q
                         net (fo=7, routed)           1.665     6.476                         sbx/D[12]
    SLICE_X57Y156        FDRE                                         r  AG_dmac/AG_ppc/AG_sbx
                                                                                              sbx/swrbusf_reg[12]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.354     3.137                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.906 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.404     3.310                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.393 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      3.004     6.397                         sbx/CLK
    SLICE_X57Y156        FDRE                                         r  AG_dmac/AG_ppc/AG_sbx
                                                                                              sbx/swrbusf_reg[12]/C
                         clock pessimism             -0.311     6.086                           
                         clock uncertainty            0.246     6.332                           
    SLICE_X57Y156        FDRE (Hold_AFF2_SLICEM_C_D)
                                                      0.107     6.439    AG_dmac/AG_ppc/AG_sbx
                                                                                                sbx/swrbusf_reg[12]
  -------------------------------------------------------------------
                         required time                         -6.439                           
                         arrival time                           6.476                           
  -------------------------------------------------------------------
                         slack                                  0.037                           





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  gclkx

Setup :            0  Failing Endpoints,  Worst Slack        3.192ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.039ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.192ns  (required time - arrival time)
  Source:                 mb/cnt/rdys[14].qrdy_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            dmac/qirdyta_reg/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        1.885ns  (logic 0.254ns (13.475%)  route 1.631ns (86.525%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.742ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.350ns
    Source Clock Delay      (SCD):    6.092ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.240ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.205ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      2.060ns (routing 0.335ns, distribution 1.725ns)
  Clock Net Delay (Destination): 1.845ns (routing 0.309ns, distribution 1.536ns)
  Timing Exception:       MaxDelay Path 6.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.509     0.510 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.090     0.600                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.600 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.750     1.350                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     1.433 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          2.310     3.743                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     3.512 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.437     3.949                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.032 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        2.060     6.092                         mb/cnt/c0_ddr4_ui_clk
    SLICE_X33Y151        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/rdys[14].qrdy_reg[14]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X33Y151        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.117     6.209 f  AG_dmac/AG_mbcnt     mb/cnt/rdys[14].qrdy_reg[14]/Q
                         net (fo=1, routed)           1.608     7.817                         dmac/qrdym[11]
    SLICE_X61Y151        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.137     7.954 r  AG_dmac              dmac/qirdyta_i_1/O
                         net (fo=1, routed)           0.023     7.977                         dmac/qirdyta0
    SLICE_X61Y151        FDRE                                         r  AG_dmac              dmac/qirdyta_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    6.000     6.000                         
    GTHE3_COMMON_X0Y2                                 0.000     6.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     6.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     6.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     6.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     8.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     9.058 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.372     9.430                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     9.505 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.845    11.350                         dmac/ioclk
    SLICE_X61Y151        FDRE                                         r  AG_dmac              dmac/qirdyta_reg/C
                         clock pessimism              0.000    11.350                           
                         clock uncertainty           -0.240    11.110                           
    SLICE_X61Y151        FDRE (Setup_FFF_SLICEM_C_D)
                                                      0.059    11.169    AG_dmac                dmac/qirdyta_reg
  -------------------------------------------------------------------
                         required time                         11.169                           
                         arrival time                          -7.977                           
  -------------------------------------------------------------------
                         slack                                  3.192                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 mb/cnt/pslot/dw_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            mb/cnt/pslot/dd/rb[3].cr/DP/I
                            (rising edge-triggered cell RAMD32 clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclkx rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.195ns  (logic 0.049ns (25.128%)  route 0.146ns (74.872%))
  Logic Levels:           0  
  Clock Path Skew:        -0.150ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.794ns
    Source Clock Delay      (SCD):    2.944ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.240ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.205ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      0.864ns (routing 0.127ns, distribution 0.737ns)
  Clock Net Delay (Destination): 1.067ns (routing 0.142ns, distribution 0.925ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r                       
    D23                                               0.000     0.000 r                       cclkp (IN)
                         net (fo=0)                   0.001     0.001                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y106
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.213     0.214 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.028     0.242                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    D23                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.242 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.350     0.592                         mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y103        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     0.619 r  AG_mb                mb/mig/inst/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.997     1.616                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.886 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.167     2.053                         mb/mig/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     2.080 r  AG_mb                mb/mig/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X0Y2 (CLOCK_ROOT)    net (fo=9656, routed)        0.864     2.944                         mb/cnt/pslot/c0_ddr4_ui_clk
    SLICE_X30Y152        FDRE                                         r  AG_mb/AG_mbasync     mb/cnt/pslot/dw_reg[3]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X30Y152        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.049     2.993 r  AG_mb/AG_mbasync     mb/cnt/pslot/dw_reg[3]/Q
                         net (fo=2, routed)           0.146     3.139                         mb/cnt/pslot/dd/rb[3].cr/D
    SLICE_X30Y151        RAMD32                                       r  AG_mb/AG_mbasync     mb/cnt/pslot/dd/rb[3].cr/DP/I
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.209     1.696                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.727 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.067     2.794                         mb/cnt/pslot/dd/rb[3].cr/WCLK
    SLICE_X30Y151        RAMD32                                       r  AG_mb/AG_mbasync     mb/cnt/pslot/dd/rb[3].cr/DP/CLK
                         clock pessimism              0.000     2.794                           
                         clock uncertainty            0.240     3.034                           
    SLICE_X30Y151        RAMD32 (Hold_E5LUT_SLICEM_CLK_I)
                                                      0.065     3.099    AG_mb/AG_mbasync       mb/cnt/pslot/dd/rb[3].cr/DP
  -------------------------------------------------------------------
                         required time                         -3.099                           
                         arrival time                           3.139                           
  -------------------------------------------------------------------
                         slack                                  0.039                           





---------------------------------------------------------------------------------------------------
From Clock:  genblk1[0].user_clk_1
  To Clock:  gclkx

Setup :            0  Failing Endpoints,  Worst Slack        2.568ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.035ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.568ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].xior/vfa/vcnt_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            nvmp/genblk1[0].xior/wfa/wtop_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        3.924ns  (logic 0.064ns (1.631%)  route 3.860ns (98.369%))
  Logic Levels:           0  
  Clock Path Skew:        1.608ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.805ns
    Source Clock Delay      (SCD):    1.197ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.032ns (routing 0.348ns, distribution 0.684ns)
  Clock Net Delay (Destination): 0.952ns (routing 0.127ns, distribution 0.825ns)
  Timing Exception:       MaxDelay Path 5.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.035     0.035                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.032     1.197                         nvmp/genblk1[0].xior/vfa/CLK_USERCLK
    SLICE_X86Y71         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].xior/vfa/vcnt_reg[8]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X86Y71         FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.064     1.261 r  AG_nvmp              nvmp/genblk1[0].xior/vfa/vcnt_reg[8]/Q
                         net (fo=9, routed)           3.860     5.121                         nvmp/genblk1[0].xior/wfa/D[4]
    SLICE_X86Y96         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].xior/wfa/wtop_reg[4]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    5.000     5.000                         
    GTHE3_COMMON_X0Y2                                 0.000     5.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     5.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     5.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     5.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     5.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     6.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     6.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     6.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     6.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.952     7.805                         nvmp/genblk1[0].xior/wfa/ioclk
    SLICE_X86Y96         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].xior/wfa/wtop_reg[4]/C
                         clock pessimism              0.000     7.805                           
                         clock uncertainty           -0.147     7.658                           
    SLICE_X86Y96         FDRE (Setup_EFF2_SLICEL_C_D)
                                                      0.031     7.689    AG_nvmp                nvmp/genblk1[0].xior/wfa/wtop_reg[4]
  -------------------------------------------------------------------
                         required time                          7.689                           
                         arrival time                          -5.121                           
  -------------------------------------------------------------------
                         slack                                  2.568                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].xior/vfa/vcnt_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            nvmp/genblk1[0].xior/wfa/wtop_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (gclkx rise@0.000ns - genblk1[0].user_clk_1 rise@0.000ns)
  Data Path Delay:        3.958ns  (logic 0.104ns (2.628%)  route 3.854ns (97.372%))
  Logic Levels:           0  
  Clock Path Skew:        3.667ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.689ns
    Source Clock Delay      (SCD):    2.022ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.693ns (routing 0.548ns, distribution 1.145ns)
  Clock Net Delay (Destination): 2.223ns (routing 0.335ns, distribution 1.888ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.046     0.046                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     0.329 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.693     2.022                         nvmp/genblk1[0].xior/vfa/CLK_USERCLK
    SLICE_X86Y74         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].xior/vfa/vcnt_reg[6]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X86Y74         FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.104     2.126 r  AG_nvmp              nvmp/genblk1[0].xior/vfa/vcnt_reg[6]/Q
                         net (fo=12, routed)          3.854     5.980                         nvmp/genblk1[0].xior/wfa/D[2]
    SLICE_X86Y96         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].xior/wfa/wtop_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.223     5.689                         nvmp/genblk1[0].xior/wfa/ioclk
    SLICE_X86Y96         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].xior/wfa/wtop_reg[2]/C
                         clock pessimism              0.000     5.689                           
                         clock uncertainty            0.147     5.836                           
    SLICE_X86Y96         FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.109     5.945    AG_nvmp                nvmp/genblk1[0].xior/wfa/wtop_reg[2]
  -------------------------------------------------------------------
                         required time                         -5.945                           
                         arrival time                           5.980                           
  -------------------------------------------------------------------
                         slack                                  0.035                           





---------------------------------------------------------------------------------------------------
From Clock:  gclkf
  To Clock:  gclkx

Setup :            0  Failing Endpoints,  Worst Slack        1.571ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.266ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.571ns  (required time - arrival time)
  Source:                 core1/noop_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Destination:            core1/wbusx_reg[41]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        3.563ns  (logic 0.302ns (8.476%)  route 3.261ns (91.524%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.681ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.390ns
    Source Clock Delay      (SCD):    6.382ns
    Clock Pessimism Removal (CPR):    0.311ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.214ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      2.989ns (routing 1.079ns, distribution 1.910ns)
  Clock Net Delay (Destination): 1.885ns (routing 0.309ns, distribution 1.576ns)
  Timing Exception:       MaxDelay Path 6.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.354     3.137                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.906 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.404     3.310                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.393 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      2.989     6.382                         core1/gclkf[0]
    SLICE_X50Y113        FDRE                                         r  AG_cores             core1/noop_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X50Y113        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.114     6.496 r  AG_cores             core1/noop_reg/Q
                         net (fo=66, routed)          3.234     9.730                         core1/fi/dps/dpw[1].sdr.inst/noop
    SLICE_X47Y159        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.188     9.918 r  AG_cores             core1/fi/dps/dpw[1].sdr.inst/wbusx[41]_i_1/O
                         net (fo=1, routed)           0.027     9.945                         core1/fi_n_27
    SLICE_X47Y159        FDRE                                         r  AG_cores             core1/wbusx_reg[41]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    6.000     6.000                         
    GTHE3_COMMON_X0Y2                                 0.000     6.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     6.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     6.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     6.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     8.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     9.058 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.372     9.430                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     9.505 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.885    11.390                         core1/ioclk
    SLICE_X47Y159        FDRE                                         r  AG_cores             core1/wbusx_reg[41]/C
                         clock pessimism              0.311    11.701                           
                         clock uncertainty           -0.244    11.457                           
    SLICE_X47Y159        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.059    11.516    AG_cores               core1/wbusx_reg[41]
  -------------------------------------------------------------------
                         required time                         11.516                           
                         arrival time                          -9.945                           
  -------------------------------------------------------------------
                         slack                                  1.571                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.266ns  (arrival time - required time)
  Source:                 core1/cor[5].p1.engi/rfp/f_o/vfa/vcnt_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Destination:            core1/cor[5].p1.engi/rfp/f_o/wfa/wtop_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclkx rise@0.000ns - gclkf rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.048ns (25.668%)  route 0.139ns (74.332%))
  Logic Levels:           0  
  Clock Path Skew:        -0.378ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.836ns
    Source Clock Delay      (SCD):    3.017ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.214ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      1.187ns (routing 0.526ns, distribution 0.661ns)
  Clock Net Delay (Destination): 1.109ns (routing 0.142ns, distribution 0.967ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.078     1.380                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.650 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.153     1.803                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.830 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      1.187     3.017                         core1/cor[5].p1.engi/rfp/f_o/vfa/gclkf[0]
    SLICE_X31Y120        FDCE                                         r  AG_cores             core1/cor[5].p1.engi/rfp/f_o/vfa/vcnt_reg[8]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X31Y120        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.048     3.065 r  AG_cores             core1/cor[5].p1.engi/rfp/f_o/vfa/vcnt_reg[8]/Q
                         net (fo=9, routed)           0.139     3.204                         core1/cor[5].p1.engi/rfp/f_o/wfa/D[1]
    SLICE_X31Y117        FDRE                                         r  AG_cores             core1/cor[5].p1.engi/rfp/f_o/wfa/wtop_reg[1]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.209     1.696                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.727 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.109     2.836                         core1/cor[5].p1.engi/rfp/f_o/wfa/ioclk
    SLICE_X31Y117        FDRE                                         r  AG_cores             core1/cor[5].p1.engi/rfp/f_o/wfa/wtop_reg[1]/C
                         clock pessimism             -0.197     2.639                           
                         clock uncertainty            0.244     2.884                           
    SLICE_X31Y117        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.055     2.939    AG_cores               core1/cor[5].p1.engi/rfp/f_o/wfa/wtop_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.939                           
                         arrival time                           3.204                           
  -------------------------------------------------------------------
                         slack                                  0.266                           





---------------------------------------------------------------------------------------------------
From Clock:  gclky
  To Clock:  gclkx

Setup :            0  Failing Endpoints,  Worst Slack        2.583ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.583ns  (required time - arrival time)
  Source:                 ppc/j1/swrbus_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            cof/ram/dpr/dpw[0].sdr.inst/r16k.ram/DINADIN[3]
                            (rising edge-triggered cell RAMB18E2 clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        3.126ns  (logic 0.118ns (3.775%)  route 3.008ns (96.225%))
  Logic Levels:           0  
  Clock Path Skew:        0.407ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.372ns
    Source Clock Delay      (SCD):    4.853ns
    Clock Pessimism Removal (CPR):    -0.112ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.218ns (routing 0.009ns, distribution 1.209ns)
  Clock Net Delay (Destination): 1.867ns (routing 0.309ns, distribution 1.558ns)
  Timing Exception:       MaxDelay Path 6.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.218     4.853                         ppc/j1/bclk
    SLICE_X58Y151        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/swrbus_reg[3]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X58Y151        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.118     4.971 r  AG_dmac/AG_ppc       ppc/j1/swrbus_reg[3]/Q
                         net (fo=7, routed)           3.008     7.979                         cof/ram/dpr/dpw[0].sdr.inst/r16k.ram_1[3]
    RAMB18_X7Y64         RAMB18E2                                     r                       cof/ram/dpr/dpw[0].sdr.inst/r16k.ram/DINADIN[3]
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    6.000     6.000                         
    GTHE3_COMMON_X0Y2                                 0.000     6.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     6.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     6.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     6.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     8.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     9.058 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.372     9.430                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     9.505 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.867    11.372                         cof/ram/dpr/dpw[0].sdr.inst/ioclk
    RAMB18_X7Y64         RAMB18E2                                     r                       cof/ram/dpr/dpw[0].sdr.inst/r16k.ram/CLKBWRCLK
                         clock pessimism             -0.112    11.260                           
                         clock uncertainty           -0.181    11.079                           
    RAMB18_X7Y64         RAMB18E2 (Setup_RAMB18E2_L_RAMB180_CLKBWRCLK_DINADIN[3])
                                                     -0.517    10.562                           cof/ram/dpr/dpw[0].sdr.inst/r16k.ram
  -------------------------------------------------------------------
                         required time                         10.562                           
                         arrival time                          -7.979                           
  -------------------------------------------------------------------
                         slack                                  2.583                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 ppc/j1/saddr_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            ppc/sadx_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclkx rise@0.000ns - gclky rise@0.000ns)
  Data Path Delay:        0.802ns  (logic 0.049ns (6.110%)  route 0.753ns (93.890%))
  Logic Levels:           0  
  Clock Path Skew:        0.535ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.699ns
    Source Clock Delay      (SCD):    2.336ns
    Clock Pessimism Removal (CPR):    -0.172ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.503ns (routing 0.007ns, distribution 0.496ns)
  Clock Net Delay (Destination): 0.972ns (routing 0.142ns, distribution 0.830ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.154     1.813                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.020     1.833 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         0.503     2.336                         ppc/j1/bclk
    SLICE_X56Y148        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/saddr_reg[17]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X56Y148        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.049     2.385 r  AG_dmac/AG_ppc       ppc/j1/saddr_reg[17]/Q
                         net (fo=2, routed)           0.753     3.138                         ppc/saddr_reg[31][11]
    SLICE_X56Y148        FDRE                                         r  AG_dmac/AG_ppc       ppc/sadx_reg[17]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.209     1.696                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.727 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.972     2.699                         ppc/ioclk
    SLICE_X56Y148        FDRE                                         r  AG_dmac/AG_ppc       ppc/sadx_reg[17]/C
                         clock pessimism              0.172     2.871                           
                         clock uncertainty            0.181     3.053                           
    SLICE_X56Y148        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.056     3.109    AG_dmac/AG_ppc         ppc/sadx_reg[17]
  -------------------------------------------------------------------
                         required time                         -3.109                           
                         arrival time                           3.138                           
  -------------------------------------------------------------------
                         slack                                  0.030                           





---------------------------------------------------------------------------------------------------
From Clock:  GTHE3_CHANNEL_RXOUTCLK[0]
  To Clock:  gclkx

Setup :            0  Failing Endpoints,  Worst Slack        4.225ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.057ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.225ns  (required time - arrival time)
  Source:                 cif/vcnt_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            cif/vcntx_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            7.000ns  (MaxDelay Path 7.000ns)
  Data Path Delay:        5.420ns  (logic 0.117ns (2.159%)  route 5.303ns (97.841%))
  Logic Levels:           0  
  Clock Path Skew:        2.732ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.323ns
    Source Clock Delay      (SCD):    2.591ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.194ns (routing 0.702ns, distribution 1.492ns)
  Clock Net Delay (Destination): 1.818ns (routing 0.309ns, distribution 1.509ns)
  Timing Exception:       MaxDelay Path 7.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        2.194     2.591                         cif/rclk1[0]
    SLICE_X55Y147        FDRE                                         r                       cif/vcnt_reg[1]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X55Y147        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.117     2.708 r                       cif/vcnt_reg[1]/Q
                         net (fo=9, routed)           5.303     8.011                         cif/cistats[17]
    SLICE_X57Y149        FDRE                                         r                       cif/vcntx_reg[1]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    7.000     7.000                         
    GTHE3_COMMON_X0Y2                                 0.000     7.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     7.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     7.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     7.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     7.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     9.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335    10.058 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.372    10.430                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075    10.505 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.818    12.323                         cif/ioclk
    SLICE_X57Y149        FDRE                                         r                       cif/vcntx_reg[1]/C
                         clock pessimism              0.000    12.323                           
                         clock uncertainty           -0.147    12.176                           
    SLICE_X57Y149        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.060    12.236                           cif/vcntx_reg[1]
  -------------------------------------------------------------------
                         required time                         12.236                           
                         arrival time                          -8.011                           
  -------------------------------------------------------------------
                         slack                                  4.225                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.057ns  (arrival time - required time)
  Source:                 hi/fab/vfa0/vcnt_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            hi/fab/wfa0/wtop_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (gclkx rise@0.000ns - GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        3.645ns  (logic 0.107ns (2.936%)  route 3.538ns (97.064%))
  Logic Levels:           0  
  Clock Path Skew:        3.332ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.564ns
    Source Clock Delay      (SCD):    2.232ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.903ns (routing 0.637ns, distribution 1.266ns)
  Clock Net Delay (Destination): 2.098ns (routing 0.335ns, distribution 1.763ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     0.046                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     0.329 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.903     2.232                         hi/fab/vfa0/rclk1[0]
    SLICE_X71Y153        FDCE                                         r  AG_riop              hi/fab/vfa0/vcnt_reg[4]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X71Y153        FDCE (Prop_CFF2_SLICEM_C_Q)
                                                      0.107     2.339 r  AG_riop              hi/fab/vfa0/vcnt_reg[4]/Q
                         net (fo=5, routed)           3.538     5.877                         hi/fab/wfa0/D[0]
    SLICE_X72Y152        FDRE                                         r  AG_riop              hi/fab/wfa0/wtop_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.098     5.564                         hi/fab/wfa0/ioclk
    SLICE_X72Y152        FDRE                                         r  AG_riop              hi/fab/wfa0/wtop_reg[0]/C
                         clock pessimism              0.000     5.564                           
                         clock uncertainty            0.147     5.711                           
    SLICE_X72Y152        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.109     5.820    AG_riop                hi/fab/wfa0/wtop_reg[0]
  -------------------------------------------------------------------
                         required time                         -5.820                           
                         arrival time                           5.877                           
  -------------------------------------------------------------------
                         slack                                  0.057                           





---------------------------------------------------------------------------------------------------
From Clock:  GTHE3_CHANNEL_TXOUTCLK[0]
  To Clock:  gclkx

Setup :            0  Failing Endpoints,  Worst Slack        4.525ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.041ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.525ns  (required time - arrival time)
  Source:                 ho/fab/wfa2/vcnt_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            ho/fab/vfa2/wtop_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            7.000ns  (MaxDelay Path 7.000ns)
  Data Path Delay:        5.180ns  (logic 0.117ns (2.259%)  route 5.063ns (97.741%))
  Logic Levels:           0  
  Clock Path Skew:        2.791ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.438ns
    Source Clock Delay      (SCD):    2.647ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.250ns (routing 0.707ns, distribution 1.543ns)
  Clock Net Delay (Destination): 1.933ns (routing 0.309ns, distribution 1.624ns)
  Timing Exception:       MaxDelay Path 7.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         2.250     2.647                         ho/fab/wfa2/rclk1__0[0]
    SLICE_X78Y139        FDCE                                         r  AG_riop              ho/fab/wfa2/vcnt_reg[8]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X78Y139        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.117     2.764 r  AG_riop              ho/fab/wfa2/vcnt_reg[8]/Q
                         net (fo=4, routed)           5.063     7.827                         ho/fab/vfa2/wtop_reg[1]_0[1]
    SLICE_X79Y140        FDRE                                         r  AG_riop              ho/fab/vfa2/wtop_reg[1]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    7.000     7.000                         
    GTHE3_COMMON_X0Y2                                 0.000     7.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     7.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     7.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     7.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     7.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     9.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335    10.058 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.372    10.430                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075    10.505 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.933    12.438                         ho/fab/vfa2/ioclk
    SLICE_X79Y140        FDRE                                         r  AG_riop              ho/fab/vfa2/wtop_reg[1]/C
                         clock pessimism              0.000    12.438                           
                         clock uncertainty           -0.147    12.291                           
    SLICE_X79Y140        FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.061    12.352    AG_riop                ho/fab/vfa2/wtop_reg[1]
  -------------------------------------------------------------------
                         required time                         12.352                           
                         arrival time                          -7.827                           
  -------------------------------------------------------------------
                         slack                                  4.525                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 ho/fab/wfa1/vcnt_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            ho/fab/vfa1/wtop_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (gclkx rise@0.000ns - GTHE3_CHANNEL_TXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        3.593ns  (logic 0.106ns (2.950%)  route 3.487ns (97.050%))
  Logic Levels:           0  
  Clock Path Skew:        3.298ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.624ns
    Source Clock Delay      (SCD):    2.326ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.997ns (routing 0.642ns, distribution 1.355ns)
  Clock Net Delay (Destination): 2.158ns (routing 0.335ns, distribution 1.823ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     0.046                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     0.329 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         1.997     2.326                         ho/fab/wfa1/rclk1__0[0]
    SLICE_X77Y138        FDCE                                         r  AG_riop              ho/fab/wfa1/vcnt_reg[8]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X77Y138        FDCE (Prop_BFF2_SLICEL_C_Q)
                                                      0.106     2.432 r  AG_riop              ho/fab/wfa1/vcnt_reg[8]/Q
                         net (fo=4, routed)           3.487     5.919                         ho/fab/vfa1/wtop_reg[1]_0[1]
    SLICE_X77Y139        FDRE                                         r  AG_riop              ho/fab/vfa1/wtop_reg[1]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.158     5.624                         ho/fab/vfa1/ioclk
    SLICE_X77Y139        FDRE                                         r  AG_riop              ho/fab/vfa1/wtop_reg[1]/C
                         clock pessimism              0.000     5.624                           
                         clock uncertainty            0.147     5.771                           
    SLICE_X77Y139        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.107     5.878    AG_riop                ho/fab/vfa1/wtop_reg[1]
  -------------------------------------------------------------------
                         required time                         -5.878                           
                         arrival time                           5.919                           
  -------------------------------------------------------------------
                         slack                                  0.041                           





---------------------------------------------------------------------------------------------------
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  gclkx

Setup :            0  Failing Endpoints,  Worst Slack        4.693ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.053ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.693ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].tfifo/wfa/vcnt_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].tfifo/vfa/wtop_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            7.000ns  (MaxDelay Path 7.000ns)
  Data Path Delay:        3.635ns  (logic 0.064ns (1.761%)  route 3.571ns (98.239%))
  Logic Levels:           0  
  Clock Path Skew:        1.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.847ns
    Source Clock Delay      (SCD):    1.404ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.239ns (routing 0.384ns, distribution 0.855ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.127ns, distribution 0.867ns)
  Timing Exception:       MaxDelay Path 7.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.239     1.404                         niop/bnk/genblk2[0].genblk1[0].tfifo/wfa/txusrclk2
    SLICE_X87Y237        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].tfifo/wfa/vcnt_reg[11]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X87Y237        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.064     1.468 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].tfifo/wfa/vcnt_reg[11]/Q
                         net (fo=7, routed)           3.571     5.039                         niop/bnk/genblk2[0].genblk1[0].tfifo/vfa/wtop_reg[4]_0[4]
    SLICE_X86Y243        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].tfifo/vfa/wtop_reg[4]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    7.000     7.000                         
    GTHE3_COMMON_X0Y2                                 0.000     7.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     7.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     7.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     7.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     7.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     8.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     8.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     8.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     8.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.994     9.847                         niop/bnk/genblk2[0].genblk1[0].tfifo/vfa/ioclk
    SLICE_X86Y243        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].tfifo/vfa/wtop_reg[4]/C
                         clock pessimism              0.000     9.847                           
                         clock uncertainty           -0.147     9.700                           
    SLICE_X86Y243        FDRE (Setup_GFF_SLICEL_C_D)
                                                      0.032     9.732    AG_niop                niop/bnk/genblk2[0].genblk1[0].tfifo/vfa/wtop_reg[4]
  -------------------------------------------------------------------
                         required time                          9.732                           
                         arrival time                          -5.039                           
  -------------------------------------------------------------------
                         slack                                  4.693                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.053ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].tfifo/wfa/vcnt_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].tfifo/vfa/wstable_reg/D
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             gclkx
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (gclkx rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        3.679ns  (logic 0.133ns (3.615%)  route 3.546ns (96.385%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        3.371ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.719ns
    Source Clock Delay      (SCD):    2.348ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.019ns (routing 0.567ns, distribution 1.452ns)
  Clock Net Delay (Destination): 2.253ns (routing 0.335ns, distribution 1.918ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     0.046                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     0.329 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.019     2.348                         niop/bnk/genblk2[0].genblk1[1].tfifo/wfa/txusrclk2
    SLICE_X85Y220        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].tfifo/wfa/vcnt_reg[6]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X85Y220        FDCE (Prop_FFF_SLICEL_C_Q)
                                                      0.104     2.452 f  AG_niop              niop/bnk/genblk2[0].genblk1[1].tfifo/wfa/vcnt_reg[6]/Q
                         net (fo=6, routed)           3.523     5.975                         niop/bnk/genblk2[0].genblk1[1].tfifo/wfa/Q[6]
    SLICE_X84Y238        LUT1 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.029     6.004 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].tfifo/wfa/wstable_i_1__141/O
                         net (fo=1, routed)           0.023     6.027                         niop/bnk/genblk2[0].genblk1[1].tfifo/vfa/p_0_in
    SLICE_X84Y238        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].tfifo/vfa/wstable_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.253     5.719                         niop/bnk/genblk2[0].genblk1[1].tfifo/vfa/ioclk
    SLICE_X84Y238        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].tfifo/vfa/wstable_reg/C
                         clock pessimism              0.000     5.719                           
                         clock uncertainty            0.147     5.866                           
    SLICE_X84Y238        FDRE (Hold_AFF_SLICEL_C_D)
                                                      0.108     5.974    AG_niop                niop/bnk/genblk2[0].genblk1[1].tfifo/vfa/wstable_reg
  -------------------------------------------------------------------
                         required time                         -5.974                           
                         arrival time                           6.027                           
  -------------------------------------------------------------------
                         slack                                  0.053                           





---------------------------------------------------------------------------------------------------
From Clock:  gclkx
  To Clock:  gclky

Setup :            0  Failing Endpoints,  Worst Slack        0.558ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.066ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.558ns  (required time - arrival time)
  Source:                 cif/ram/dpr/dpw[0].sdr.inst/r16k.ram/CLKARDCLK
                            (rising edge-triggered cell RAMB18E2 clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            ppc/j1/mstkx/m/outr_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             gclky
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.282ns  (logic 1.704ns (39.794%)  route 2.578ns (60.206%))
  Logic Levels:           5  (LUT3=2 LUT6=3)
  Clock Path Skew:        -1.038ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.726ns
    Source Clock Delay      (SCD):    5.652ns
    Clock Pessimism Removal (CPR):    -0.112ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      2.186ns (routing 0.335ns, distribution 1.851ns)
  Clock Net Delay (Destination): 1.088ns (routing 0.009ns, distribution 1.079ns)
  Timing Exception:       MaxDelay Path 6.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.186     5.652                         cif/ram/dpr/dpw[0].sdr.inst/ioclk
    RAMB18_X5Y60         RAMB18E2                                     r                       cif/ram/dpr/dpw[0].sdr.inst/r16k.ram/CLKARDCLK
  -------------------------------------------------------------------    ----------------------------------------
    RAMB18_X5Y60         RAMB18E2 (Prop_RAMB18E2_L_RAMB180_CLKARDCLK_DOUTBDOUT[3])
                                                      1.272     6.924 r                       cif/ram/dpr/dpw[0].sdr.inst/r16k.ram/DOUTBDOUT[3]
                         net (fo=1, routed)           1.182     8.106                         cif/ram/dpr/dpw[0].sdr.inst/cidata[21]
    SLICE_X55Y153        LUT3 (Prop_D5LUT_SLICEM_I2_O)
                                                      0.210     8.316 r                       cif/ram/dpr/dpw[0].sdr.inst/outr[21]_i_10/O
                         net (fo=1, routed)           0.318     8.634                         ppc/j1/mstkx/m/srdbusha[21]
    SLICE_X56Y154        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.040     8.674 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[21]_i_6/O
                         net (fo=1, routed)           0.345     9.019                         ppc/j1/mstkx/m/outr[21]_i_6_n_0
    SLICE_X57Y156        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.071     9.090 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[21]_i_5/O
                         net (fo=1, routed)           0.126     9.216                         ppc/j1/mstkx/m/outr[21]_i_5_n_0
    SLICE_X57Y156        LUT3 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.040     9.256 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[21]_i_2__1/O
                         net (fo=1, routed)           0.580     9.836                         ppc/j1/ncr1.code/dpw[0].sdr.inst/srdbus[21]
    SLICE_X59Y145        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.071     9.907 r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/outr[21]_i_1__1/O
                         net (fo=1, routed)           0.027     9.934                         ppc/j1/mstkx/m/outp[21]
    SLICE_X59Y145        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr_reg[21]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    6.000     6.000                         
    GTHE3_COMMON_X0Y2                                 0.000     6.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     6.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     6.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     6.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     8.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335     9.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356     9.414                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224     9.638 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.088    10.726                         ppc/j1/mstkx/m/bclk
    SLICE_X59Y145        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr_reg[21]/C
                         clock pessimism             -0.112    10.614                           
                         clock uncertainty           -0.181    10.433                           
    SLICE_X59Y145        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.059    10.492    AG_dmac/AG_ppc         ppc/j1/mstkx/m/outr_reg[21]
  -------------------------------------------------------------------
                         required time                         10.492                           
                         arrival time                          -9.934                           
  -------------------------------------------------------------------
                         slack                                  0.558                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.066ns  (arrival time - required time)
  Source:                 ppc/j1/ireq_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            ppc/j1/req_reg/D
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             gclky
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclky rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.227ns  (logic 0.105ns (46.256%)  route 0.122ns (53.744%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.076ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.433ns
    Source Clock Delay      (SCD):    2.681ns
    Clock Pessimism Removal (CPR):    -0.172ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.828ns (routing 0.127ns, distribution 0.701ns)
  Clock Net Delay (Destination): 0.615ns (routing 0.008ns, distribution 0.607ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.828     2.681                         ppc/j1/ioclk
    SLICE_X56Y140        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/ireq_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X56Y140        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.048     2.729 f  AG_dmac/AG_ppc       ppc/j1/ireq_reg/Q
                         net (fo=5, routed)           0.110     2.839                         ppc/j1/ireq_reg_0
    SLICE_X55Y139        LUT5 (Prop_H5LUT_SLICEM_I1_O)
                                                      0.057     2.896 r  AG_dmac/AG_ppc       ppc/j1/req_i_1/O
                         net (fo=1, routed)           0.012     2.908                         ppc/j1/req0
    SLICE_X55Y139        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/req_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.210     1.697                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.121     1.818 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         0.615     2.433                         ppc/j1/bclk
    SLICE_X55Y139        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/req_reg/C
                         clock pessimism              0.172     2.605                           
                         clock uncertainty            0.181     2.787                           
    SLICE_X55Y139        FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.056     2.843    AG_dmac/AG_ppc         ppc/j1/req_reg
  -------------------------------------------------------------------
                         required time                         -2.843                           
                         arrival time                           2.908                           
  -------------------------------------------------------------------
                         slack                                  0.066                           





---------------------------------------------------------------------------------------------------
From Clock:  gclks
  To Clock:  gclky

Setup :            0  Failing Endpoints,  Worst Slack        0.142ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.640ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.142ns  (required time - arrival time)
  Source:                 niop/bnk/srdbus_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ppc/j1/mstkx/m/outr_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             gclky
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (gclky rise@5.000ns - gclks rise@0.000ns)
  Data Path Delay:        3.553ns  (logic 0.417ns (11.737%)  route 3.136ns (88.263%))
  Logic Levels:           4  (LUT3=1 LUT4=1 LUT6=2)
  Clock Path Skew:        -1.302ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.740ns = ( 9.740 - 5.000 ) 
    Source Clock Delay      (SCD):    5.940ns
    Clock Pessimism Removal (CPR):    -0.102ns
  Clock Uncertainty:      0.061ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.305ns (routing 0.353ns, distribution 1.952ns)
  Clock Net Delay (Destination): 1.102ns (routing 0.009ns, distribution 1.093ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.305     5.940                         niop/bnk/gclks
    SLICE_X88Y232        FDRE                                         r  AG_niop              niop/bnk/srdbus_reg[18]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X88Y232        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.114     6.054 r  AG_niop              niop/bnk/srdbus_reg[18]/Q
                         net (fo=1, routed)           1.696     7.750                         mcore1/ss/sbdp/outr[31]_i_8__0_0[18]
    SLICE_X57Y185        LUT4 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.073     7.823 r  AG_cores             mcore1/ss/sbdp/outr[18]_i_8/O
                         net (fo=1, routed)           0.581     8.404                         ppc/j1/mstkx/m/outr[18]_i_2__1_1
    SLICE_X56Y155        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.041     8.445 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[18]_i_5/O
                         net (fo=1, routed)           0.278     8.723                         ppc/j1/mstkx/m/outr[18]_i_5_n_0
    SLICE_X56Y155        LUT3 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.115     8.838 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[18]_i_2__1/O
                         net (fo=1, routed)           0.555     9.393                         ppc/j1/ncr1.code/dpw[0].sdr.inst/srdbus[18]
    SLICE_X58Y142        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.074     9.467 r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/outr[18]_i_1__1/O
                         net (fo=1, routed)           0.026     9.493                         ppc/j1/mstkx/m/outp[18]
    SLICE_X58Y142        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr_reg[18]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclky rise edge)      5.000     5.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     5.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     5.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     5.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     5.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     5.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     7.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335     8.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356     8.414                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224     8.638 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.102     9.740                         ppc/j1/mstkx/m/bclk
    SLICE_X58Y142        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr_reg[18]/C
                         clock pessimism             -0.102     9.638                           
                         clock uncertainty           -0.061     9.577                           
    SLICE_X58Y142        FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.058     9.635    AG_dmac/AG_ppc         ppc/j1/mstkx/m/outr_reg[18]
  -------------------------------------------------------------------
                         required time                          9.635                           
                         arrival time                          -9.493                           
  -------------------------------------------------------------------
                         slack                                  0.142                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.640ns  (arrival time - required time)
  Source:                 riop/nolabel_line97/m/outr_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ppc/j1/mstkx/m/outr_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             gclky
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclky rise@0.000ns - gclks rise@0.000ns)
  Data Path Delay:        0.591ns  (logic 0.195ns (32.995%)  route 0.396ns (67.005%))
  Logic Levels:           4  (LUT3=1 LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.105ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.420ns
    Source Clock Delay      (SCD):    2.684ns
    Clock Pessimism Removal (CPR):    -0.159ns
  Clock Net Delay (Source):      0.851ns (routing 0.135ns, distribution 0.716ns)
  Clock Net Delay (Destination): 0.602ns (routing 0.008ns, distribution 0.594ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.154     1.813                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.020     1.833 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        0.851     2.684                         riop/nolabel_line97/m/gclks
    SLICE_X59Y155        FDRE                                         r  AG_riop              riop/nolabel_line97/m/outr_reg[31]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X59Y155        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.049     2.733 r  AG_riop              riop/nolabel_line97/m/outr_reg[31]/Q
                         net (fo=1, routed)           0.035     2.768                         riop/nolabel_line97/m/srdbusr[31]
    SLICE_X59Y155        LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.045     2.813 r  AG_riop              riop/nolabel_line97/m/outr[31]_i_13/O
                         net (fo=1, routed)           0.079     2.892                         ppc/j1/mstkx/m/outr[31]_i_2__2_0
    SLICE_X58Y155        LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.071     2.963 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[31]_i_8__0/O
                         net (fo=1, routed)           0.133     3.096                         ppc/j1/mstkx/m/outr[31]_i_8__0_n_0
    SLICE_X58Y152        LUT3 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.015     3.111 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[31]_i_2__2/O
                         net (fo=1, routed)           0.133     3.244                         ppc/j1/ncr1.code/dpw[0].sdr.inst/srdbus[31]
    SLICE_X58Y146        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.015     3.259 r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/outr[31]_i_1__1/O
                         net (fo=1, routed)           0.016     3.275                         ppc/j1/mstkx/m/outp[31]
    SLICE_X58Y146        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr_reg[31]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.210     1.697                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.121     1.818 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         0.602     2.420                         ppc/j1/mstkx/m/bclk
    SLICE_X58Y146        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr_reg[31]/C
                         clock pessimism              0.159     2.579                           
    SLICE_X58Y146        FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.056     2.635    AG_dmac/AG_ppc         ppc/j1/mstkx/m/outr_reg[31]
  -------------------------------------------------------------------
                         required time                         -2.635                           
                         arrival time                           3.275                           
  -------------------------------------------------------------------
                         slack                                  0.640                           





---------------------------------------------------------------------------------------------------
From Clock:  GTHE3_CHANNEL_RXOUTCLK[0]
  To Clock:  gclky

Setup :            0  Failing Endpoints,  Worst Slack        4.147ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.039ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.147ns  (required time - arrival time)
  Source:                 cif/vcnt_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            ppc/j1/mstkx/m/outr_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             gclky
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        3.909ns  (logic 0.467ns (11.947%)  route 3.442ns (88.053%))
  Logic Levels:           5  (LUT3=2 LUT5=1 LUT6=2)
  Clock Path Skew:        2.145ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.736ns
    Source Clock Delay      (SCD):    2.591ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.194ns (routing 0.702ns, distribution 1.492ns)
  Clock Net Delay (Destination): 1.098ns (routing 0.009ns, distribution 1.089ns)
  Timing Exception:       MaxDelay Path 6.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        2.194     2.591                         cif/rclk1[0]
    SLICE_X55Y147        FDRE                                         r                       cif/vcnt_reg[0]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X55Y147        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.114     2.705 r                       cif/vcnt_reg[0]/Q
                         net (fo=10, routed)          1.808     4.513                         cif/ram/dpr/dpw[0].sdr.inst/r16k.ram_0[0]
    SLICE_X55Y151        LUT3 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.118     4.631 r                       cif/ram/dpr/dpw[0].sdr.inst/outr[16]_i_10/O
                         net (fo=1, routed)           0.338     4.969                         ppc/j1/mstkx/m/srdbusha[16]
    SLICE_X55Y149        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.040     5.009 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[16]_i_6/O
                         net (fo=1, routed)           0.426     5.435                         ppc/j1/mstkx/m/outr[16]_i_6_n_0
    SLICE_X57Y149        LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.040     5.475 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[16]_i_5/O
                         net (fo=1, routed)           0.391     5.866                         ppc/j1/mstkx/m/outr[16]_i_5_n_0
    SLICE_X57Y147        LUT3 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.115     5.981 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[16]_i_2__1/O
                         net (fo=1, routed)           0.450     6.431                         ppc/j1/ncr1.code/dpw[0].sdr.inst/srdbus[16]
    SLICE_X59Y142        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     6.471 r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/outr[16]_i_1__1/O
                         net (fo=1, routed)           0.029     6.500                         ppc/j1/mstkx/m/outp[16]
    SLICE_X59Y142        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr_reg[16]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    6.000     6.000                         
    GTHE3_COMMON_X0Y2                                 0.000     6.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     6.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     6.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     6.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     8.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335     9.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356     9.414                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224     9.638 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.098    10.736                         ppc/j1/mstkx/m/bclk
    SLICE_X59Y142        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr_reg[16]/C
                         clock pessimism              0.000    10.736                           
                         clock uncertainty           -0.149    10.588                           
    SLICE_X59Y142        FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.059    10.647    AG_dmac/AG_ppc         ppc/j1/mstkx/m/outr_reg[16]
  -------------------------------------------------------------------
                         required time                         10.647                           
                         arrival time                          -6.500                           
  -------------------------------------------------------------------
                         slack                                  4.147                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 cif/vcnt_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            ppc/j1/mstkx/m/outr_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             gclky
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (gclky rise@0.000ns - GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        2.913ns  (logic 0.481ns (16.512%)  route 2.432ns (83.488%))
  Logic Levels:           5  (LUT3=2 LUT5=1 LUT6=2)
  Clock Path Skew:        2.618ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.887ns
    Source Clock Delay      (SCD):    2.269ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.940ns (routing 0.637ns, distribution 1.303ns)
  Clock Net Delay (Destination): 1.252ns (routing 0.009ns, distribution 1.243ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     0.046                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     0.329 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.940     2.269                         cif/rclk1[0]
    SLICE_X56Y147        FDRE                                         r                       cif/vcnt_reg[7]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X56Y147        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.104     2.373 r                       cif/vcnt_reg[7]/Q
                         net (fo=5, routed)           1.250     3.623                         cif/ram/dpr/dpw[0].sdr.inst/r16k.ram_0[7]
    SLICE_X55Y151        LUT3 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.073     3.696 r                       cif/ram/dpr/dpw[0].sdr.inst/outr[23]_i_10/O
                         net (fo=1, routed)           0.171     3.867                         ppc/j1/mstkx/m/srdbusha[23]
    SLICE_X55Y151        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.126     3.993 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[23]_i_6/O
                         net (fo=1, routed)           0.251     4.244                         ppc/j1/mstkx/m/outr[23]_i_6_n_0
    SLICE_X55Y156        LUT5 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.092     4.336 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[23]_i_5/O
                         net (fo=1, routed)           0.260     4.596                         ppc/j1/mstkx/m/outr[23]_i_5_n_0
    SLICE_X56Y156        LUT3 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.057     4.653 r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr[23]_i_2__1/O
                         net (fo=1, routed)           0.471     5.124                         ppc/j1/ncr1.code/dpw[0].sdr.inst/srdbus[23]
    SLICE_X58Y144        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.029     5.153 r  AG_dmac/AG_ppc       ppc/j1/ncr1.code/dpw[0].sdr.inst/outr[23]_i_1__1/O
                         net (fo=1, routed)           0.029     5.182                         ppc/j1/mstkx/m/outp[23]
    SLICE_X58Y144        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr_reg[23]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.252     4.887                         ppc/j1/mstkx/m/bclk
    SLICE_X58Y144        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/mstkx/m/outr_reg[23]/C
                         clock pessimism              0.000     4.887                           
                         clock uncertainty            0.149     5.036                           
    SLICE_X58Y144        FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.107     5.143    AG_dmac/AG_ppc         ppc/j1/mstkx/m/outr_reg[23]
  -------------------------------------------------------------------
                         required time                         -5.143                           
                         arrival time                           5.182                           
  -------------------------------------------------------------------
                         slack                                  0.039                           





---------------------------------------------------------------------------------------------------
From Clock:  gclkx
  To Clock:  gclks

Setup :            0  Failing Endpoints,  Worst Slack        1.800ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.039ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.800ns  (required time - arrival time)
  Source:                 sc/rprc_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            niop/bnk/oauxf_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             gclks
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        3.863ns  (logic 0.246ns (6.368%)  route 3.617ns (93.632%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.073ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.595ns
    Source Clock Delay      (SCD):    5.556ns
    Clock Pessimism Removal (CPR):    -0.112ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      2.090ns (routing 0.335ns, distribution 1.755ns)
  Clock Net Delay (Destination): 1.957ns (routing 0.326ns, distribution 1.631ns)
  Timing Exception:       MaxDelay Path 6.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.090     5.556                         sc/ioclk
    SLICE_X59Y129        FDRE                                         r                       sc/rprc_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X59Y129        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     5.670 r                       sc/rprc_reg/Q
                         net (fo=122, routed)         2.148     7.818                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/areset_rxusrclk2_sync_i/riox
    SLICE_X95Y156        LUT2 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.132     7.950 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/areset_rxusrclk2_sync_i/sync1_r[4]_i_1__7/O
                         net (fo=93, routed)          1.469     9.419                         niop/bnk/arst
    SLICE_X82Y137        FDRE                                         r  AG_niop              niop/bnk/oauxf_reg[2]/R
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    6.000     6.000                         
    GTHE3_COMMON_X0Y2                                 0.000     6.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     6.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     6.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     6.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     8.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335     9.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356     9.414                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224     9.638 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        1.957    11.595                         niop/bnk/gclks
    SLICE_X82Y137        FDRE                                         r  AG_niop              niop/bnk/oauxf_reg[2]/C
                         clock pessimism             -0.112    11.483                           
                         clock uncertainty           -0.181    11.302                           
    SLICE_X82Y137        FDRE (Setup_EFF_SLICEM_C_R)
                                                     -0.083    11.219    AG_niop                niop/bnk/oauxf_reg[2]
  -------------------------------------------------------------------
                         required time                         11.219                           
                         arrival time                          -9.419                           
  -------------------------------------------------------------------
                         slack                                  1.800                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 ppc/sadx_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            sbx/sads_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             gclks
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclks rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.577ns  (logic 0.049ns (8.492%)  route 0.528ns (91.508%))
  Logic Levels:           0  
  Clock Path Skew:        0.301ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.817ns
    Source Clock Delay      (SCD):    2.688ns
    Clock Pessimism Removal (CPR):    -0.172ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.835ns (routing 0.127ns, distribution 0.708ns)
  Clock Net Delay (Destination): 0.999ns (routing 0.151ns, distribution 0.848ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.835     2.688                         ppc/ioclk
    SLICE_X55Y156        FDRE                                         r  AG_dmac/AG_ppc       ppc/sadx_reg[20]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X55Y156        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.049     2.737 r  AG_dmac/AG_ppc       ppc/sadx_reg[20]/Q
                         net (fo=1, routed)           0.528     3.265                         sbx/sads_reg[31]_0[20]
    SLICE_X57Y160        FDRE                                         r  AG_dmac/AG_ppc/AG_sbx
                                                                                              sbx/sads_reg[20]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.210     1.697                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.121     1.818 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        0.999     2.817                         sbx/gclks
    SLICE_X57Y160        FDRE                                         r  AG_dmac/AG_ppc/AG_sbx
                                                                                              sbx/sads_reg[20]/C
                         clock pessimism              0.172     2.989                           
                         clock uncertainty            0.181     3.171                           
    SLICE_X57Y160        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.056     3.227    AG_dmac/AG_ppc/AG_sbx
                                                                                                sbx/sads_reg[20]
  -------------------------------------------------------------------
                         required time                         -3.227                           
                         arrival time                           3.265                           
  -------------------------------------------------------------------
                         slack                                  0.039                           





---------------------------------------------------------------------------------------------------
From Clock:  gclky
  To Clock:  gclks

Setup :            0  Failing Endpoints,  Worst Slack        2.531ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.036ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.531ns  (required time - arrival time)
  Source:                 ppc/j1/swrbus_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            sc/srcfg_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             gclks
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (gclks rise@10.000ns - gclky rise@5.000ns)
  Data Path Delay:        2.988ns  (logic 0.118ns (3.949%)  route 2.870ns (96.051%))
  Logic Levels:           0  
  Clock Path Skew:        0.520ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.469ns = ( 15.469 - 10.000 ) 
    Source Clock Delay      (SCD):    4.847ns = ( 9.847 - 5.000 ) 
    Clock Pessimism Removal (CPR):    -0.102ns
  Clock Uncertainty:      0.061ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.212ns (routing 0.009ns, distribution 1.203ns)
  Clock Net Delay (Destination): 1.831ns (routing 0.326ns, distribution 1.505ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclky rise edge)      5.000     5.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     5.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     5.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     5.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     5.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     5.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     8.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     7.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     8.353                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     8.635 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.212     9.847                         ppc/j1/bclk
    SLICE_X57Y147        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/swrbus_reg[4]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X57Y147        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.118     9.965 r  AG_dmac/AG_ppc       ppc/j1/swrbus_reg[4]/Q
                         net (fo=7, routed)           2.870    12.835                         sc/rmemy_reg_0[4]
    SLICE_X57Y147        FDRE                                         r                       sc/srcfg_reg[4]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclks rise edge)     10.000    10.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r                       qclkp (IN)
                         net (fo=0)                   0.000    10.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230    10.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046    10.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283    10.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164    12.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335    13.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356    13.414                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224    13.638 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        1.831    15.469                         sc/gclks
    SLICE_X57Y147        FDRE                                         r                       sc/srcfg_reg[4]/C
                         clock pessimism             -0.102    15.367                           
                         clock uncertainty           -0.061    15.306                           
    SLICE_X57Y147        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.060    15.366                           sc/srcfg_reg[4]
  -------------------------------------------------------------------
                         required time                         15.366                           
                         arrival time                         -12.835                           
  -------------------------------------------------------------------
                         slack                                  2.531                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 ppc/j1/swrbus_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            sc/srcfg_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             gclks
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (gclks rise@0.000ns - gclky rise@0.000ns)
  Data Path Delay:        1.233ns  (logic 0.104ns (8.435%)  route 1.129ns (91.565%))
  Logic Levels:           0  
  Clock Path Skew:        1.088ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.694ns
    Source Clock Delay      (SCD):    4.708ns
    Clock Pessimism Removal (CPR):    -0.102ns
  Clock Net Delay (Source):      1.070ns (routing 0.009ns, distribution 1.061ns)
  Clock Net Delay (Destination): 2.059ns (routing 0.353ns, distribution 1.706ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclky rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     0.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     0.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     0.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     2.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335     3.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356     3.414                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224     3.638 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         1.070     4.708                         ppc/j1/bclk
    SLICE_X56Y148        FDRE                                         r  AG_dmac/AG_ppc       ppc/j1/swrbus_reg[20]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X56Y148        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.104     4.812 r  AG_dmac/AG_ppc       ppc/j1/swrbus_reg[20]/Q
                         net (fo=6, routed)           1.129     5.941                         sc/rmemy_reg_0[20]
    SLICE_X56Y153        FDRE                                         r                       sc/srcfg_reg[20]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.059     5.694                         sc/gclks
    SLICE_X56Y153        FDRE                                         r                       sc/srcfg_reg[20]/C
                         clock pessimism              0.102     5.796                           
    SLICE_X56Y153        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.109     5.905                           sc/srcfg_reg[20]
  -------------------------------------------------------------------
                         required time                         -5.905                           
                         arrival time                           5.941                           
  -------------------------------------------------------------------
                         slack                                  0.036                           





---------------------------------------------------------------------------------------------------
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  gclks

Setup :            0  Failing Endpoints,  Worst Slack        3.233ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.035ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.233ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].p2d/s_sblk/ram/CLKARDCLK
                            (rising edge-triggered cell RAMB36E2 clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/srdbus_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             gclks
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            7.000ns  (MaxDelay Path 7.000ns)
  Data Path Delay:        6.574ns  (logic 1.441ns (21.920%)  route 5.133ns (78.080%))
  Logic Levels:           2  (LUT6=1 MUXF7=1)
  Clock Path Skew:        2.896ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.652ns
    Source Clock Delay      (SCD):    2.756ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.359ns (routing 0.623ns, distribution 1.736ns)
  Clock Net Delay (Destination): 2.014ns (routing 0.326ns, distribution 1.688ns)
  Timing Exception:       MaxDelay Path 7.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.359     2.756                         niop/bnk/genblk2[0].genblk1[1].p2d/s_sblk/txusrclk2
    RAMB36_X9Y46         RAMB36E2                                     r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/s_sblk/ram/CLKARDCLK
  -------------------------------------------------------------------    ----------------------------------------
    RAMB36_X9Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKARDCLK_DOUTADOUT[25])
                                                      1.259     4.015 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/s_sblk/ram/DOUTADOUT[25]
                         net (fo=1, routed)           5.093     9.108                         niop/bnk/genblk2[0].genblk1[2].p2d/s_sblk/srdbus_reg[31][25]
    SLICE_X85Y232        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.115     9.223 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/s_sblk/srdbus[25]_i_3/O
                         net (fo=1, routed)           0.000     9.223                         niop/bnk/genblk2[0].genblk1[2].d2p/rhdr/dpw[0].sdr.inst/srdbusj[25]
    SLICE_X85Y232        MUXF7 (Prop_F7MUX_CD_SLICEL_I1_O)
                                                      0.067     9.290 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].d2p/rhdr/dpw[0].sdr.inst/srdbus_reg[25]_i_1/O
                         net (fo=1, routed)           0.040     9.330                         niop/bnk/genblk2[0].genblk1[2].d2p_n_6
    SLICE_X85Y232        FDRE                                         r  AG_niop              niop/bnk/srdbus_reg[25]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    7.000     7.000                         
    GTHE3_COMMON_X0Y2                                 0.000     7.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     7.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     7.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     7.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     7.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     9.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335    10.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356    10.414                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224    10.638 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.014    12.652                         niop/bnk/gclks
    SLICE_X85Y232        FDRE                                         r  AG_niop              niop/bnk/srdbus_reg[25]/C
                         clock pessimism              0.000    12.652                           
                         clock uncertainty           -0.149    12.504                           
    SLICE_X85Y232        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.059    12.563    AG_niop                niop/bnk/srdbus_reg[25]
  -------------------------------------------------------------------
                         required time                         12.563                           
                         arrival time                          -9.330                           
  -------------------------------------------------------------------
                         slack                                  3.233                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].p2d/s_sblk/ram/CLKARDCLK
                            (rising edge-triggered cell RAMB36E2 clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/srdbus_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             gclks
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (gclks rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        3.828ns  (logic 0.670ns (17.503%)  route 3.158ns (82.497%))
  Logic Levels:           2  (LUT6=1 MUXF7=1)
  Clock Path Skew:        3.536ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.899ns
    Source Clock Delay      (SCD):    2.363ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.034ns (routing 0.567ns, distribution 1.467ns)
  Clock Net Delay (Destination): 2.264ns (routing 0.353ns, distribution 1.911ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     0.046                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     0.329 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.034     2.363                         niop/bnk/genblk2[0].genblk1[3].p2d/s_sblk/txusrclk2
    RAMB36_X9Y53         RAMB36E2                                     r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/s_sblk/ram/CLKARDCLK
  -------------------------------------------------------------------    ----------------------------------------
    RAMB36_X9Y53         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKARDCLK_DOUTADOUT[13])
                                                      0.570     2.933 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/s_sblk/ram/DOUTADOUT[13]
                         net (fo=1, routed)           3.140     6.073                         niop/bnk/genblk2[0].genblk1[2].p2d/s_sblk/s_rdbus[13]
    SLICE_X85Y232        LUT6 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.056     6.129 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/s_sblk/srdbus[13]_i_3/O
                         net (fo=1, routed)           0.000     6.129                         niop/bnk/genblk2[0].genblk1[2].d2p/rhdr/dpw[0].sdr.inst/srdbusj[13]
    SLICE_X85Y232        MUXF7 (Prop_F7MUX_EF_SLICEL_I1_O)
                                                      0.044     6.173 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].d2p/rhdr/dpw[0].sdr.inst/srdbus_reg[13]_i_1/O
                         net (fo=1, routed)           0.018     6.191                         niop/bnk/genblk2[0].genblk1[2].d2p_n_18
    SLICE_X85Y232        FDRE                                         r  AG_niop              niop/bnk/srdbus_reg[13]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.264     5.899                         niop/bnk/gclks
    SLICE_X85Y232        FDRE                                         r  AG_niop              niop/bnk/srdbus_reg[13]/C
                         clock pessimism              0.000     5.899                           
                         clock uncertainty            0.149     6.048                           
    SLICE_X85Y232        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.108     6.156    AG_niop                niop/bnk/srdbus_reg[13]
  -------------------------------------------------------------------
                         required time                         -6.156                           
                         arrival time                           6.191                           
  -------------------------------------------------------------------
                         slack                                  0.035                           





---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
  To Clock:  lclks

Setup :            0  Failing Endpoints,  Worst Slack       32.128ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             32.128ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {rise@0.000ns fall@16.500ns period=33.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             lclks
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.000ns  (MaxDelay Path 33.000ns)
  Data Path Delay:        0.932ns  (logic 0.114ns (12.232%)  route 0.818ns (87.768%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 33.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y161                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X35Y161        FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.114     0.114 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.818     0.932    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X36Y163        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   33.000    33.000    
    SLICE_X36Y163        FDCE (Setup_HFF2_SLICEM_C_D)
                                                      0.060    33.060    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         33.060    
                         arrival time                          -0.932    
  -------------------------------------------------------------------
                         slack                                 32.128    





---------------------------------------------------------------------------------------------------
From Clock:  gclks
  To Clock:  lclks

Setup :            0  Failing Endpoints,  Worst Slack        7.015ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.274ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.015ns  (required time - arrival time)
  Source:                 sc/srcfg_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mb/cnt/refena_reg/D
                            (rising edge-triggered cell FDRE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             lclks
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (lclks rise@10.000ns - gclks rise@0.000ns)
  Data Path Delay:        2.343ns  (logic 0.480ns (20.487%)  route 1.863ns (79.513%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        -0.516ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.292ns = ( 15.292 - 10.000 ) 
    Source Clock Delay      (SCD):    5.696ns
    Clock Pessimism Removal (CPR):    -0.112ns
  Clock Uncertainty:      0.187ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      2.061ns (routing 0.353ns, distribution 1.708ns)
  Clock Net Delay (Destination): 1.787ns (routing 0.683ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.061     5.696                         sc/gclks
    SLICE_X55Y150        FDRE                                         r                       sc/srcfg_reg[10]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X55Y150        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.115     5.811 f                       sc/srcfg_reg[10]/Q
                         net (fo=6, routed)           1.397     7.208                         sc/gclkms[12]
    SLICE_X34Y150        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.174     7.382 r                       sc/refena_i_2/O
                         net (fo=1, routed)           0.429     7.811                         sc/refena_i_2_n_0
    SLICE_X33Y147        LUT3 (Prop_G5LUT_SLICEL_I2_O)
                                                      0.191     8.002 r                       sc/refena_i_1/O
                         net (fo=1, routed)           0.037     8.039                         mb/cnt/refena_reg_0
    SLICE_X33Y147        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/refena_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock lclks rise edge)     10.000    10.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r                       qclkp (IN)
                         net (fo=0)                   0.000    10.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230    10.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046    10.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283    10.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164    12.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                      0.335    13.058 r                       sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         0.372    13.430                         sc/lclks
    BUFGCE_X1Y51         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075    13.505 r                       sc/_clkm/O
    X1Y2 (CLOCK_ROOT)    net (fo=13, routed)          1.787    15.292                         mb/cnt/gclkms[1]
    SLICE_X33Y147        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/refena_reg/C
                         clock pessimism             -0.112    15.180                           
                         clock uncertainty           -0.187    14.993                           
    SLICE_X33Y147        FDRE (Setup_GFF2_SLICEL_C_D)
                                                      0.061    15.054    AG_dmac/AG_mbcnt       mb/cnt/refena_reg
  -------------------------------------------------------------------
                         required time                         15.054                           
                         arrival time                          -8.039                           
  -------------------------------------------------------------------
                         slack                                  7.015                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.274ns  (arrival time - required time)
  Source:                 sc/srcfg_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mb/cnt/refena_reg/D
                            (rising edge-triggered cell FDRE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             lclks
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (lclks rise@0.000ns - gclks rise@0.000ns)
  Data Path Delay:        0.782ns  (logic 0.103ns (13.171%)  route 0.679ns (86.829%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.265ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.757ns
    Source Clock Delay      (SCD):    2.664ns
    Clock Pessimism Removal (CPR):    -0.172ns
  Clock Uncertainty:      0.187ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.831ns (routing 0.135ns, distribution 0.696ns)
  Clock Net Delay (Destination): 1.030ns (routing 0.400ns, distribution 0.630ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.154     1.813                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.020     1.833 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        0.831     2.664                         sc/gclks
    SLICE_X55Y151        FDRE                                         r                       sc/srcfg_reg[9]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X55Y151        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.048     2.712 f                       sc/srcfg_reg[9]/Q
                         net (fo=6, routed)           0.667     3.379                         sc/gclkms[11]
    SLICE_X33Y147        LUT3 (Prop_G5LUT_SLICEL_I0_O)
                                                      0.055     3.434 r                       sc/refena_i_1/O
                         net (fo=1, routed)           0.012     3.446                         mb/cnt/refena_reg_0
    SLICE_X33Y147        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/refena_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock lclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         0.209     1.696                         sc/lclks
    BUFGCE_X1Y51         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.727 r                       sc/_clkm/O
    X1Y2 (CLOCK_ROOT)    net (fo=13, routed)          1.030     2.757                         mb/cnt/gclkms[1]
    SLICE_X33Y147        FDRE                                         r  AG_dmac/AG_mbcnt     mb/cnt/refena_reg/C
                         clock pessimism              0.172     2.929                           
                         clock uncertainty            0.187     3.117                           
    SLICE_X33Y147        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.056     3.173    AG_dmac/AG_mbcnt       mb/cnt/refena_reg
  -------------------------------------------------------------------
                         required time                         -3.173                           
                         arrival time                           3.446                           
  -------------------------------------------------------------------
                         slack                                  0.274                           





---------------------------------------------------------------------------------------------------
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  rclkp

Setup :            0  Failing Endpoints,  Worst Slack        1.743ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.047ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.743ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/rxusrclk2_coreclk_resyncs_i/resynch[0].synch_inst/q_reg/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/sync1_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rclkp rise@6.400ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@3.200ns)
  Data Path Delay:        0.865ns  (logic 0.114ns (13.179%)  route 0.751ns (86.821%))
  Logic Levels:           0  
  Clock Path Skew:        -0.616ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.084ns = ( 8.484 - 6.400 ) 
    Source Clock Delay      (SCD):    2.700ns = ( 5.900 - 3.200 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.303ns (routing 0.623ns, distribution 1.680ns)
  Clock Net Delay (Destination): 1.551ns (routing 0.441ns, distribution 1.110ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     3.282                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     3.597 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.303     5.900                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/rxusrclk2_coreclk_resyncs_i/resynch[0].synch_inst/coreclk
    SLICE_X98Y224        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/rxusrclk2_coreclk_resyncs_i/resynch[0].synch_inst/q_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X98Y224        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     6.014 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/rxusrclk2_coreclk_resyncs_i/resynch[0].synch_inst/q_reg/Q
                         net (fo=1, routed)           0.751     6.765                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/sync1_r_reg[0]_0[0]
    SLICE_X94Y210        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/sync1_r_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      6.400     6.400 r                       
    GTHE3_COMMON_X0Y1                                 0.000     6.400 r                       rclkp (IN)
                         net (fo=0)                   0.000     6.400                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.204     6.604 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.046     6.650                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.933 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.551     8.484                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/CLK
    SLICE_X94Y210        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     8.484                           
                         clock uncertainty           -0.035     8.448                           
    SLICE_X94Y210        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.060     8.508    AG_niop                niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/block_lock_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                          8.508                           
                         arrival time                          -6.765                           
  -------------------------------------------------------------------
                         slack                                  1.743                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.047ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_txresetdone_reg1_reg/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_txresetdone_i_sync_i/sync1_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rclkp rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.269ns  (logic 0.049ns (18.216%)  route 0.220ns (81.784%))
  Logic Levels:           0  
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.347ns
    Source Clock Delay      (SCD):    1.181ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.063ns (routing 0.339ns, distribution 0.724ns)
  Clock Net Delay (Destination): 0.934ns (routing 0.289ns, distribution 0.645ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.063     1.181                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/txusrclk2
    SLICE_X96Y130        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_txresetdone_reg1_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y130        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.049     1.230 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_txresetdone_reg1_reg/Q
                         net (fo=1, routed)           0.220     1.450                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_txresetdone_i_sync_i/D[0]
    SLICE_X92Y129        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_txresetdone_i_sync_i/sync1_r_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.248     0.248 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.035     0.283                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.413 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.934     1.347                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_txresetdone_i_sync_i/CLK
    SLICE_X92Y129        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_txresetdone_i_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     1.347                           
    SLICE_X92Y129        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.056     1.403    AG_niop                niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_txresetdone_i_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.403                           
                         arrival time                           1.450                           
  -------------------------------------------------------------------
                         slack                                  0.047                           





---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk
  To Clock:  rclkp

Setup :            0  Failing Endpoints,  Worst Slack        1.922ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.045ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.922ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_reg1_reg/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/sync1_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rclkp rise@6.400ns - rxoutclk rise@3.200ns)
  Data Path Delay:        0.796ns  (logic 0.116ns (14.573%)  route 0.680ns (85.427%))
  Logic Levels:           0  
  Clock Path Skew:        -0.506ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.081ns = ( 8.481 - 6.400 ) 
    Source Clock Delay      (SCD):    2.587ns = ( 5.787 - 3.200 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.190ns (routing 0.560ns, distribution 1.630ns)
  Clock Net Delay (Destination): 1.548ns (routing 0.441ns, distribution 1.107ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     3.282                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     3.597 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        2.190     5.787                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/clk
    SLICE_X94Y133        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_reg1_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X94Y133        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.116     5.903 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_reg1_reg/Q
                         net (fo=1, routed)           0.680     6.583                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/sync1_r_reg[0]_0[0]
    SLICE_X93Y129        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/sync1_r_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      6.400     6.400 r                       
    GTHE3_COMMON_X0Y1                                 0.000     6.400 r                       rclkp (IN)
                         net (fo=0)                   0.000     6.400                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.204     6.604 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.046     6.650                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.933 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.548     8.481                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/CLK
    SLICE_X93Y129        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     8.481                           
                         clock uncertainty           -0.035     8.445                           
    SLICE_X93Y129        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.060     8.505    AG_niop                niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                          8.505                           
                         arrival time                          -6.583                           
  -------------------------------------------------------------------
                         slack                                  1.922                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.045ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_reg/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/sync1_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rclkp rise@0.000ns - rxoutclk rise@0.000ns)
  Data Path Delay:        0.306ns  (logic 0.049ns (16.013%)  route 0.257ns (83.987%))
  Logic Levels:           0  
  Clock Path Skew:        0.205ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.329ns
    Source Clock Delay      (SCD):    1.124ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.006ns (routing 0.314ns, distribution 0.692ns)
  Clock Net Delay (Destination): 0.916ns (routing 0.289ns, distribution 0.627ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.006     1.124                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/CLK
    SLICE_X94Y133        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X94Y133        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.049     1.173 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_reg/Q
                         net (fo=4, routed)           0.257     1.430                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/D[0]
    SLICE_X93Y139        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/sync1_r_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.248     0.248 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.035     0.283                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.413 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.916     1.329                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/data_out_reg_0
    SLICE_X93Y139        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     1.329                           
    SLICE_X93Y139        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.056     1.385    AG_niop                niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.385                           
                         arrival time                           1.430                           
  -------------------------------------------------------------------
                         slack                                  0.045                           





---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk_1
  To Clock:  rclkp

Setup :            0  Failing Endpoints,  Worst Slack        1.834ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.093ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.834ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_reg1_reg/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/sync1_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rclkp rise@6.400ns - rxoutclk_1 rise@3.200ns)
  Data Path Delay:        1.402ns  (logic 0.114ns (8.131%)  route 1.288ns (91.869%))
  Logic Levels:           0  
  Clock Path Skew:        0.012ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.080ns = ( 8.480 - 6.400 ) 
    Source Clock Delay      (SCD):    2.068ns = ( 5.268 - 3.200 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.671ns (routing 0.414ns, distribution 1.257ns)
  Clock Net Delay (Destination): 1.547ns (routing 0.441ns, distribution 1.106ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_1 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     3.282                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     3.597 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.671     5.268                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/clk
    SLICE_X93Y145        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_reg1_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X93Y145        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     5.382 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_reg1_reg/Q
                         net (fo=1, routed)           1.288     6.670                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/sync1_r_reg[0]_0[0]
    SLICE_X87Y145        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/sync1_r_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      6.400     6.400 r                       
    GTHE3_COMMON_X0Y1                                 0.000     6.400 r                       rclkp (IN)
                         net (fo=0)                   0.000     6.400                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.204     6.604 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.046     6.650                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.933 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.547     8.480                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/CLK
    SLICE_X87Y145        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     8.480                           
                         clock uncertainty           -0.035     8.444                           
    SLICE_X87Y145        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.060     8.504    AG_niop                niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                          8.504                           
                         arrival time                          -6.670                           
  -------------------------------------------------------------------
                         slack                                  1.834                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.093ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_reg/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/sync1_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rclkp rise@0.000ns - rxoutclk_1 rise@0.000ns)
  Data Path Delay:        0.628ns  (logic 0.048ns (7.643%)  route 0.580ns (92.357%))
  Logic Levels:           0  
  Clock Path Skew:        0.479ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.323ns
    Source Clock Delay      (SCD):    0.844ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.726ns (routing 0.222ns, distribution 0.504ns)
  Clock Net Delay (Destination): 0.910ns (routing 0.289ns, distribution 0.621ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        0.726     0.844                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/CLK
    SLICE_X99Y148        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X99Y148        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.048     0.892 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_reg/Q
                         net (fo=7, routed)           0.580     1.472                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/D[0]
    SLICE_X100Y146       FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/sync1_r_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.248     0.248 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.035     0.283                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.413 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.910     1.323                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/data_out_reg_0
    SLICE_X100Y146       FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     1.323                           
    SLICE_X100Y146       FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.056     1.379    AG_niop                niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.379                           
                         arrival time                           1.472                           
  -------------------------------------------------------------------
                         slack                                  0.093                           





---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk_2
  To Clock:  rclkp

Setup :            0  Failing Endpoints,  Worst Slack        1.782ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.105ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.782ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/cable_pull_reg/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/sync1_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rclkp rise@6.400ns - rxoutclk_2 rise@3.200ns)
  Data Path Delay:        1.027ns  (logic 0.114ns (11.100%)  route 0.913ns (88.900%))
  Logic Levels:           0  
  Clock Path Skew:        -0.415ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.100ns = ( 8.500 - 6.400 ) 
    Source Clock Delay      (SCD):    2.515ns = ( 5.715 - 3.200 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.118ns (routing 0.584ns, distribution 1.534ns)
  Clock Net Delay (Destination): 1.567ns (routing 0.441ns, distribution 1.126ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     3.282                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     3.597 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        2.118     5.715                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rxusrclk2
    SLICE_X97Y199        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/cable_pull_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X97Y199        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.114     5.829 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/cable_pull_reg/Q
                         net (fo=2, routed)           0.913     6.742                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/D[0]
    SLICE_X92Y180        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/sync1_r_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      6.400     6.400 r                       
    GTHE3_COMMON_X0Y1                                 0.000     6.400 r                       rclkp (IN)
                         net (fo=0)                   0.000     6.400                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.204     6.604 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.046     6.650                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.933 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.567     8.500                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/CLK
    SLICE_X92Y180        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     8.500                           
                         clock uncertainty           -0.035     8.464                           
    SLICE_X92Y180        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.060     8.524    AG_niop                niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                          8.524                           
                         arrival time                          -6.742                           
  -------------------------------------------------------------------
                         slack                                  1.782                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.105ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_reg/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/sync1_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rclkp rise@0.000ns - rxoutclk_2 rise@0.000ns)
  Data Path Delay:        0.423ns  (logic 0.049ns (11.584%)  route 0.374ns (88.416%))
  Logic Levels:           0  
  Clock Path Skew:        0.262ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.341ns
    Source Clock Delay      (SCD):    1.079ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.961ns (routing 0.304ns, distribution 0.657ns)
  Clock Net Delay (Destination): 0.928ns (routing 0.289ns, distribution 0.639ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        0.961     1.079                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/CLK
    SLICE_X98Y161        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X98Y161        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.049     1.128 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_reg/Q
                         net (fo=4, routed)           0.374     1.502                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/D[0]
    SLICE_X96Y160        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/sync1_r_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.248     0.248 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.035     0.283                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.413 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.928     1.341                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/data_out_reg_0
    SLICE_X96Y160        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     1.341                           
    SLICE_X96Y160        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.056     1.397    AG_niop                niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.397                           
                         arrival time                           1.502                           
  -------------------------------------------------------------------
                         slack                                  0.105                           





---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk_3
  To Clock:  rclkp

Setup :            0  Failing Endpoints,  Worst Slack        1.855ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.050ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.855ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_reg/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/sync1_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rclkp rise@6.400ns - rxoutclk_3 rise@3.200ns)
  Data Path Delay:        1.061ns  (logic 0.114ns (10.745%)  route 0.947ns (89.255%))
  Logic Levels:           0  
  Clock Path Skew:        -0.308ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.081ns = ( 8.481 - 6.400 ) 
    Source Clock Delay      (SCD):    2.389ns = ( 5.589 - 3.200 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.992ns (routing 0.575ns, distribution 1.417ns)
  Clock Net Delay (Destination): 1.548ns (routing 0.441ns, distribution 1.107ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_3 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     3.282                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     3.597 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.992     5.589                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/CLK
    SLICE_X98Y176        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X98Y176        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.114     5.703 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_reg/Q
                         net (fo=7, routed)           0.947     6.650                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/D[0]
    SLICE_X94Y173        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/sync1_r_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      6.400     6.400 r                       
    GTHE3_COMMON_X0Y1                                 0.000     6.400 r                       rclkp (IN)
                         net (fo=0)                   0.000     6.400                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.204     6.604 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.046     6.650                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.933 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.548     8.481                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/data_out_reg_0
    SLICE_X94Y173        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     8.481                           
                         clock uncertainty           -0.035     8.445                           
    SLICE_X94Y173        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.060     8.505    AG_niop                niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                          8.505                           
                         arrival time                          -6.650                           
  -------------------------------------------------------------------
                         slack                                  1.855                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.050ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/cable_pull_reg/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/sync1_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             rclkp
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rclkp rise@0.000ns - rxoutclk_3 rise@0.000ns)
  Data Path Delay:        0.441ns  (logic 0.048ns (10.884%)  route 0.393ns (89.116%))
  Logic Levels:           0  
  Clock Path Skew:        0.335ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.339ns
    Source Clock Delay      (SCD):    1.004ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.886ns (routing 0.302ns, distribution 0.584ns)
  Clock Net Delay (Destination): 0.926ns (routing 0.289ns, distribution 0.637ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_3 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        0.886     1.004                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/rxusrclk2
    SLICE_X99Y231        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/cable_pull_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X99Y231        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.048     1.052 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER32.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rx_pcs_fsm_i/cable_pull_reg/Q
                         net (fo=2, routed)           0.393     1.445                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/D[0]
    SLICE_X96Y209        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/sync1_r_reg[0]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.248     0.248 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.035     0.283                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.413 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.926     1.339                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/CLK
    SLICE_X96Y209        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     1.339                           
    SLICE_X96Y209        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.056     1.395    AG_niop                niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_coreclk_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.395                           
                         arrival time                           1.445                           
  -------------------------------------------------------------------
                         slack                                  0.050                           





---------------------------------------------------------------------------------------------------
From Clock:  gclkx
  To Clock:  GTHE3_CHANNEL_RXOUTCLK[0]

Setup :            0  Failing Endpoints,  Worst Slack        1.507ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.412ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.507ns  (required time - arrival time)
  Source:                 cmdrst_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            cif/vcnt_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             GTHE3_CHANNEL_RXOUTCLK[0]
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            7.000ns  (MaxDelay Path 7.000ns)
  Data Path Delay:        1.879ns  (logic 0.115ns (6.120%)  route 1.764ns (93.880%))
  Logic Levels:           0  
  Clock Path Skew:        -3.383ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.270ns
    Source Clock Delay      (SCD):    5.653ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.187ns (routing 0.335ns, distribution 1.852ns)
  Clock Net Delay (Destination): 1.941ns (routing 0.637ns, distribution 1.304ns)
  Timing Exception:       MaxDelay Path 7.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.187     5.653                         ioclk
    SLICE_X82Y118        FDRE                                         r                       cmdrst_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X82Y118        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.115     5.768 r                       cmdrst_reg/Q
                         net (fo=55, routed)          1.764     7.532                         cif/SR[0]
    SLICE_X56Y146        FDRE                                         r                       cif/vcnt_reg[2]/R
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    7.000     7.000                         
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     7.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     7.046                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     7.329 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.941     9.270                         cif/rclk1[0]
    SLICE_X56Y146        FDRE                                         r                       cif/vcnt_reg[2]/C
                         clock pessimism              0.000     9.270                           
                         clock uncertainty           -0.147     9.123                           
    SLICE_X56Y146        FDRE (Setup_DFF_SLICEL_C_R)
                                                     -0.084     9.039                           cif/vcnt_reg[2]
  -------------------------------------------------------------------
                         required time                          9.039                           
                         arrival time                          -7.532                           
  -------------------------------------------------------------------
                         slack                                  1.507                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.412ns  (arrival time - required time)
  Source:                 dmac/hpchn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            hi/qhi/icycle_reg/D
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             GTHE3_CHANNEL_RXOUTCLK[0]
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.206ns  (logic 0.064ns (31.068%)  route 0.142ns (68.932%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -1.409ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.302ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.858ns (routing 0.127ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.137ns (routing 0.422ns, distribution 0.715ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.858     2.711                         dmac/ioclk
    SLICE_X73Y150        FDRE                                         r  AG_dmac              dmac/hpchn_reg[0]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X73Y150        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.049     2.760 r  AG_dmac              dmac/hpchn_reg[0]/Q
                         net (fo=10, routed)          0.126     2.886                         hi/qhi/SR[0]
    SLICE_X73Y147        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.015     2.901 r  AG_riop              hi/qhi/icycle_i_1/O
                         net (fo=1, routed)           0.016     2.917                         hi/qhi/icycle_i_1_n_0
    SLICE_X73Y147        FDRE                                         r  AG_riop              hi/qhi/icycle_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.137     1.302                         hi/qhi/rclk1[0]
    SLICE_X73Y147        FDRE                                         r  AG_riop              hi/qhi/icycle_reg/C
                         clock pessimism              0.000     1.302                           
                         clock uncertainty            0.147     1.449                           
    SLICE_X73Y147        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.056     1.505    AG_riop                hi/qhi/icycle_reg
  -------------------------------------------------------------------
                         required time                         -1.505                           
                         arrival time                           2.917                           
  -------------------------------------------------------------------
                         slack                                  1.412                           





---------------------------------------------------------------------------------------------------
From Clock:  gclkx
  To Clock:  GTHE3_CHANNEL_TXOUTCLK[0]

Setup :            0  Failing Endpoints,  Worst Slack        1.455ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.356ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.455ns  (required time - arrival time)
  Source:                 sc/rio_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            ho/fab/wfa1/vcnt_reg[2]/CLR
                            (rising edge-triggered cell FDCE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             GTHE3_CHANNEL_TXOUTCLK[0]
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            7.000ns  (MaxDelay Path 7.000ns)
  Data Path Delay:        1.927ns  (logic 0.117ns (6.072%)  route 1.810ns (93.928%))
  Logic Levels:           0  
  Clock Path Skew:        -3.389ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.326ns
    Source Clock Delay      (SCD):    5.715ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.249ns (routing 0.335ns, distribution 1.914ns)
  Clock Net Delay (Destination): 1.997ns (routing 0.642ns, distribution 1.355ns)
  Timing Exception:       MaxDelay Path 7.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.249     5.715                         sc/ioclk
    SLICE_X88Y129        FDRE                                         r                       sc/rio_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X88Y129        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.117     5.832 f                       sc/rio_reg/Q
                         net (fo=187, routed)         1.810     7.642                         ho/fab/wfa1/AR[0]
    SLICE_X77Y138        FDCE                                         f  AG_riop              ho/fab/wfa1/vcnt_reg[2]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    7.000     7.000                         
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     7.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     7.046                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     7.329 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         1.997     9.326                         ho/fab/wfa1/rclk1__0[0]
    SLICE_X77Y138        FDCE                                         r  AG_riop              ho/fab/wfa1/vcnt_reg[2]/C
                         clock pessimism              0.000     9.326                           
                         clock uncertainty           -0.147     9.179                           
    SLICE_X77Y138        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.082     9.097    AG_riop                ho/fab/wfa1/vcnt_reg[2]
  -------------------------------------------------------------------
                         required time                          9.097                           
                         arrival time                          -7.642                           
  -------------------------------------------------------------------
                         slack                                  1.455                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.356ns  (arrival time - required time)
  Source:                 ho/fab/vfa1/vcnt_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            ho/fab/wfa1/wtop_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             GTHE3_CHANNEL_TXOUTCLK[0]
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (GTHE3_CHANNEL_TXOUTCLK[0] rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.164ns  (logic 0.049ns (29.878%)  route 0.115ns (70.122%))
  Logic Levels:           0  
  Clock Path Skew:        -1.394ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.363ns
    Source Clock Delay      (SCD):    2.757ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.904ns (routing 0.127ns, distribution 0.777ns)
  Clock Net Delay (Destination): 1.198ns (routing 0.423ns, distribution 0.775ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.904     2.757                         ho/fab/vfa1/ioclk
    SLICE_X76Y142        FDCE                                         r  AG_riop              ho/fab/vfa1/vcnt_reg[6]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X76Y142        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.049     2.806 r  AG_riop              ho/fab/vfa1/vcnt_reg[6]/Q
                         net (fo=6, routed)           0.115     2.921                         ho/fab/wfa1/wtop_reg[4]_0[3]
    SLICE_X76Y140        FDRE                                         r  AG_riop              ho/fab/wfa1/wtop_reg[3]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         1.198     1.363                         ho/fab/wfa1/rclk1__0[0]
    SLICE_X76Y140        FDRE                                         r  AG_riop              ho/fab/wfa1/wtop_reg[3]/C
                         clock pessimism              0.000     1.363                           
                         clock uncertainty            0.147     1.510                           
    SLICE_X76Y140        FDRE (Hold_FFF2_SLICEM_C_D)
                                                      0.055     1.565    AG_riop                ho/fab/wfa1/wtop_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.565                           
                         arrival time                           2.921                           
  -------------------------------------------------------------------
                         slack                                  1.356                           





---------------------------------------------------------------------------------------------------
From Clock:  GTHE3_CHANNEL_RXOUTCLK[0]
  To Clock:  GTHE3_CHANNEL_TXOUTCLK[0]

Setup :            0  Failing Endpoints,  Worst Slack        2.495ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.054ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.495ns  (required time - arrival time)
  Source:                 riop/rbus1_reg[129]/C
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            ho/qho/ahold_reg/D
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             GTHE3_CHANNEL_TXOUTCLK[0]
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.267ns  (GTHE3_CHANNEL_TXOUTCLK[0] rise@4.267ns - GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        1.480ns  (logic 0.523ns (35.338%)  route 0.957ns (64.662%))
  Logic Levels:           2  (LUT5=2)
  Clock Path Skew:        -0.316ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.329ns = ( 6.596 - 4.267 ) 
    Source Clock Delay      (SCD):    2.645ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.248ns (routing 0.702ns, distribution 1.546ns)
  Clock Net Delay (Destination): 2.000ns (routing 0.642ns, distribution 1.358ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        2.248     2.645                         riop/rclk1[0]
    SLICE_X80Y136        FDRE                                         r  AG_riop              riop/rbus1_reg[129]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X80Y136        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.117     2.762 r  AG_riop              riop/rbus1_reg[129]/Q
                         net (fo=9, routed)           0.568     3.330                         ho/qho/ahold_reg_0[0]
    SLICE_X78Y134        LUT5 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.196     3.526 r  AG_riop              ho/qho/ahold_i_2/O
                         net (fo=1, routed)           0.354     3.880                         ho/qho/ahold_i_2_n_0
    SLICE_X78Y133        LUT5 (Prop_H5LUT_SLICEM_I3_O)
                                                      0.210     4.090 r  AG_riop              ho/qho/ahold_i_1/O
                         net (fo=1, routed)           0.035     4.125                         ho/qho/ahold0
    SLICE_X78Y133        FDRE                                         r  AG_riop              ho/qho/ahold_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      4.267     4.267 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     4.267 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     4.313                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.596 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         2.000     6.596                         ho/qho/rclk1__0[0]
    SLICE_X78Y133        FDRE                                         r  AG_riop              ho/qho/ahold_reg/C
                         clock pessimism              0.000     6.596                           
                         clock uncertainty           -0.035     6.560                           
    SLICE_X78Y133        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.060     6.620    AG_riop                ho/qho/ahold_reg
  -------------------------------------------------------------------
                         required time                          6.620                           
                         arrival time                          -4.125                           
  -------------------------------------------------------------------
                         slack                                  2.495                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.054ns  (arrival time - required time)
  Source:                 riop/rbus1_reg[129]/C
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            ho/qho/oseq_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             GTHE3_CHANNEL_TXOUTCLK[0]
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (GTHE3_CHANNEL_TXOUTCLK[0] rise@0.000ns - GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        0.301ns  (logic 0.048ns (15.947%)  route 0.253ns (84.053%))
  Logic Levels:           0  
  Clock Path Skew:        0.242ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.372ns
    Source Clock Delay      (SCD):    1.130ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.012ns (routing 0.371ns, distribution 0.641ns)
  Clock Net Delay (Destination): 1.207ns (routing 0.423ns, distribution 0.784ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.012     1.130                         riop/rclk1[0]
    SLICE_X80Y136        FDRE                                         r  AG_riop              riop/rbus1_reg[129]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X80Y136        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.048     1.178 f  AG_riop              riop/rbus1_reg[129]/Q
                         net (fo=9, routed)           0.253     1.431                         ho/qho/oseq_reg[0]_0[0]
    SLICE_X80Y132        FDRE                                         r  AG_riop              ho/qho/oseq_reg[0]/R  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         1.207     1.372                         ho/qho/rclk1__0[0]
    SLICE_X80Y132        FDRE                                         r  AG_riop              ho/qho/oseq_reg[0]/C
                         clock pessimism              0.000     1.372                           
    SLICE_X80Y132        FDRE (Hold_DFF_SLICEL_C_R)
                                                      0.005     1.377    AG_riop                ho/qho/oseq_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.377                           
                         arrival time                           1.431                           
  -------------------------------------------------------------------
                         slack                                  0.054                           





---------------------------------------------------------------------------------------------------
From Clock:  gclkx
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :            0  Failing Endpoints,  Worst Slack        0.165ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.377ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.165ns  (required time - arrival time)
  Source:                 sc/rprc_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].p2d/c_wok_reg/S
                            (rising edge-triggered cell FDSE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            7.000ns  (MaxDelay Path 7.000ns)
  Data Path Delay:        3.409ns  (logic 0.114ns (3.344%)  route 3.295ns (96.656%))
  Logic Levels:           0  
  Clock Path Skew:        -3.196ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.360ns
    Source Clock Delay      (SCD):    5.556ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.090ns (routing 0.335ns, distribution 1.755ns)
  Clock Net Delay (Destination): 2.031ns (routing 0.567ns, distribution 1.464ns)
  Timing Exception:       MaxDelay Path 7.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.090     5.556                         sc/ioclk
    SLICE_X59Y129        FDRE                                         r                       sc/rprc_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X59Y129        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     5.670 r                       sc/rprc_reg/Q
                         net (fo=122, routed)         3.295     8.965                         niop/bnk/genblk2[0].genblk1[3].p2d/riox
    SLICE_X91Y263        FDSE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/c_wok_reg/S
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    7.000     7.000                         
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     7.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     7.046                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     7.329 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.031     9.360                         niop/bnk/genblk2[0].genblk1[3].p2d/txusrclk2
    SLICE_X91Y263        FDSE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/c_wok_reg/C
                         clock pessimism              0.000     9.360                           
                         clock uncertainty           -0.147     9.213                           
    SLICE_X91Y263        FDSE (Setup_HFF_SLICEL_C_S)
                                                     -0.083     9.130    AG_niop                niop/bnk/genblk2[0].genblk1[3].p2d/c_wok_reg
  -------------------------------------------------------------------
                         required time                          9.130                           
                         arrival time                          -8.965                           
  -------------------------------------------------------------------
                         slack                                  0.165                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.377ns  (arrival time - required time)
  Source:                 niop/bnk/ofifo/wfa/vcnt_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            niop/bnk/ofifo/vfa/wtop_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.186ns  (logic 0.048ns (25.806%)  route 0.138ns (74.194%))
  Logic Levels:           0  
  Clock Path Skew:        -1.393ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.395ns
    Source Clock Delay      (SCD):    2.788ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.935ns (routing 0.127ns, distribution 0.808ns)
  Clock Net Delay (Destination): 1.230ns (routing 0.384ns, distribution 0.846ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.935     2.788                         niop/bnk/ofifo/wfa/ioclk
    SLICE_X85Y132        FDCE                                         r  AG_niop              niop/bnk/ofifo/wfa/vcnt_reg[6]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X85Y132        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.048     2.836 r  AG_niop              niop/bnk/ofifo/wfa/vcnt_reg[6]/Q
                         net (fo=9, routed)           0.138     2.974                         niop/bnk/ofifo/vfa/wtop_reg[3]_0[2]
    SLICE_X86Y132        FDRE                                         r  AG_niop              niop/bnk/ofifo/vfa/wtop_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.230     1.395                         niop/bnk/ofifo/vfa/txusrclk2
    SLICE_X86Y132        FDRE                                         r  AG_niop              niop/bnk/ofifo/vfa/wtop_reg[2]/C
                         clock pessimism              0.000     1.395                           
                         clock uncertainty            0.147     1.542                           
    SLICE_X86Y132        FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.055     1.597    AG_niop                niop/bnk/ofifo/vfa/wtop_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.597                           
                         arrival time                           2.974                           
  -------------------------------------------------------------------
                         slack                                  1.377                           





---------------------------------------------------------------------------------------------------
From Clock:  gclks
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :            0  Failing Endpoints,  Worst Slack        0.390ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.327ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.390ns  (required time - arrival time)
  Source:                 sbx/sads_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            niop/bnk/taddr_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            7.000ns  (MaxDelay Path 7.000ns)
  Data Path Delay:        3.192ns  (logic 0.114ns (3.571%)  route 3.078ns (96.429%))
  Logic Levels:           0  
  Clock Path Skew:        -3.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.363ns
    Source Clock Delay      (SCD):    5.692ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.057ns (routing 0.353ns, distribution 1.704ns)
  Clock Net Delay (Destination): 2.034ns (routing 0.567ns, distribution 1.467ns)
  Timing Exception:       MaxDelay Path 7.000ns

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.057     5.692                         sbx/gclks
    SLICE_X54Y155        FDRE                                         r  AG_dmac/AG_ppc/AG_sbx
                                                                                              sbx/sads_reg[12]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X54Y155        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     5.806 r  AG_dmac/AG_ppc/AG_sbx
                                                                                              sbx/sads_reg[12]/Q
                         net (fo=66, routed)          3.078     8.884                         niop/bnk/taddr_reg[15]_0[12]
    SLICE_X88Y233        FDRE                                         r  AG_niop              niop/bnk/taddr_reg[12]/D
  -------------------------------------------------------------------    ----------------------------------------

                         max delay                    7.000     7.000                         
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     7.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     7.046                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     7.329 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.034     9.363                         niop/bnk/txusrclk2
    SLICE_X88Y233        FDRE                                         r  AG_niop              niop/bnk/taddr_reg[12]/C
                         clock pessimism              0.000     9.363                           
                         clock uncertainty           -0.149     9.214                           
    SLICE_X88Y233        FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.060     9.274    AG_niop                niop/bnk/taddr_reg[12]
  -------------------------------------------------------------------
                         required time                          9.274                           
                         arrival time                          -8.884                           
  -------------------------------------------------------------------
                         slack                                  0.390                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.327ns  (arrival time - required time)
  Source:                 niop/bnk/oauxf_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            niop/bnk/noaux_reg/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - gclks rise@0.000ns)
  Data Path Delay:        0.154ns  (logic 0.064ns (41.558%)  route 0.090ns (58.442%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.377ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.371ns
    Source Clock Delay      (SCD):    2.748ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.915ns (routing 0.135ns, distribution 0.780ns)
  Clock Net Delay (Destination): 1.206ns (routing 0.384ns, distribution 0.822ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.154     1.813                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.020     1.833 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        0.915     2.748                         niop/bnk/gclks
    SLICE_X82Y142        FDRE                                         r  AG_niop              niop/bnk/oauxf_reg[1]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X82Y142        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.048     2.796 f  AG_niop              niop/bnk/oauxf_reg[1]/Q
                         net (fo=3, routed)           0.074     2.870                         niop/bnk/oauxf_reg_n_0_[1]
    SLICE_X82Y143        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.016     2.886 r  AG_niop              niop/bnk/noaux_i_1/O
                         net (fo=1, routed)           0.016     2.902                         niop/bnk/noaux_i_1_n_0
    SLICE_X82Y143        FDRE                                         r  AG_niop              niop/bnk/noaux_reg/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.206     1.371                         niop/bnk/txusrclk2
    SLICE_X82Y143        FDRE                                         r  AG_niop              niop/bnk/noaux_reg/C
                         clock pessimism              0.000     1.371                           
                         clock uncertainty            0.149     1.520                           
    SLICE_X82Y143        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.056     1.576    AG_niop                niop/bnk/noaux_reg
  -------------------------------------------------------------------
                         required time                         -1.576                           
                         arrival time                           2.902                           
  -------------------------------------------------------------------
                         slack                                  1.327                           





---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :            0  Failing Endpoints,  Worst Slack        1.121ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.048ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.121ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vcnt_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/wrdx_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@3.200ns - rxoutclk rise@0.000ns)
  Data Path Delay:        1.925ns  (logic 0.668ns (34.701%)  route 1.257ns (65.299%))
  Logic Levels:           3  (CARRY8=2 LUT3=1)
  Clock Path Skew:        -0.178ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.381ns = ( 5.581 - 3.200 ) 
    Source Clock Delay      (SCD):    2.559ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.162ns (routing 0.560ns, distribution 1.602ns)
  Clock Net Delay (Destination): 2.052ns (routing 0.567ns, distribution 1.485ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        2.162     2.559                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/clk
    SLICE_X90Y179        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vcnt_reg[3]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X90Y179        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.114     2.673 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vcnt_reg[3]/Q
                         net (fo=6, routed)           0.674     3.347                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vcnt_reg[3]
    SLICE_X89Y179        CARRY8 (Prop_CARRY8_SLICEL_DI[2]_CO[7])
                                                      0.342     3.689 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/odif_carry/CO[7]
                         net (fo=1, routed)           0.027     3.716                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/odif_carry_n_0
    SLICE_X89Y180        CARRY8 (Prop_CARRY8_SLICEL_CI_O[4])
                                                      0.141     3.857 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/odif_carry__0/O[4]
                         net (fo=1, routed)           0.529     4.386                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/odif0_out[13]
    SLICE_X89Y182        LUT3 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.071     4.457 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/wrdx[2]_i_1/O
                         net (fo=1, routed)           0.027     4.484                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/p_1_out[2]
    SLICE_X89Y182        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/wrdx_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.052     5.581                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/txusrclk2
    SLICE_X89Y182        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/wrdx_reg[2]/C
                         clock pessimism              0.000     5.581                           
                         clock uncertainty           -0.035     5.546                           
    SLICE_X89Y182        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.059     5.605    AG_niop                niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/wrdx_reg[2]
  -------------------------------------------------------------------
                         required time                          5.605                           
                         arrival time                          -4.484                           
  -------------------------------------------------------------------
                         slack                                  1.121                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.048ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].p2d/p_i/wfa/wtop_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - rxoutclk rise@0.000ns)
  Data Path Delay:        0.408ns  (logic 0.048ns (11.765%)  route 0.360ns (88.235%))
  Logic Levels:           0  
  Clock Path Skew:        0.305ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.408ns
    Source Clock Delay      (SCD):    1.103ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.985ns (routing 0.314ns, distribution 0.671ns)
  Clock Net Delay (Destination): 1.243ns (routing 0.384ns, distribution 0.859ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        0.985     1.103                         niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/clk
    SLICE_X84Y199        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[3]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X84Y199        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.048     1.151 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[3]/Q
                         net (fo=6, routed)           0.360     1.511                         niop/bnk/genblk2[0].genblk1[0].p2d/p_i/wfa/wtop_reg[8]_0[3]
    SLICE_X84Y198        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/p_i/wfa/wtop_reg[3]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.243     1.408                         niop/bnk/genblk2[0].genblk1[0].p2d/p_i/wfa/txusrclk2
    SLICE_X84Y198        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/p_i/wfa/wtop_reg[3]/C
                         clock pessimism              0.000     1.408                           
    SLICE_X84Y198        FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.055     1.463    AG_niop                niop/bnk/genblk2[0].genblk1[0].p2d/p_i/wfa/wtop_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.463                           
                         arrival time                           1.511                           
  -------------------------------------------------------------------
                         slack                                  0.048                           





---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk_1
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :            0  Failing Endpoints,  Worst Slack        1.245ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.076ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.245ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/vcnt_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/wrdx_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@3.200ns - rxoutclk_1 rise@0.000ns)
  Data Path Delay:        2.227ns  (logic 0.493ns (22.137%)  route 1.734ns (77.863%))
  Logic Levels:           2  (CARRY8=1 LUT3=1)
  Clock Path Skew:        0.248ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.377ns = ( 5.577 - 3.200 ) 
    Source Clock Delay      (SCD):    2.129ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.732ns (routing 0.414ns, distribution 1.318ns)
  Clock Net Delay (Destination): 2.048ns (routing 0.567ns, distribution 1.481ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.732     2.129                         niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/clk
    SLICE_X91Y222        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/vcnt_reg[11]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y222        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.114     2.243 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/vcnt_reg[11]/Q
                         net (fo=6, routed)           1.229     3.472                         niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/vcnt_reg[11]
    SLICE_X92Y222        CARRY8 (Prop_CARRY8_SLICEL_DI[2]_O[4])
                                                      0.249     3.721 f  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/odif_carry__0/O[4]
                         net (fo=1, routed)           0.476     4.197                         niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/odif0_out[13]
    SLICE_X92Y217        LUT3 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.130     4.327 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/wrdx[2]_i_1__0/O
                         net (fo=1, routed)           0.029     4.356                         niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/p_1_out[2]
    SLICE_X92Y217        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/wrdx_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.048     5.577                         niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/txusrclk2
    SLICE_X92Y217        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/wrdx_reg[2]/C
                         clock pessimism              0.000     5.577                           
                         clock uncertainty           -0.035     5.542                           
    SLICE_X92Y217        FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.059     5.601    AG_niop                niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/wrdx_reg[2]
  -------------------------------------------------------------------
                         required time                          5.601                           
                         arrival time                          -4.356                           
  -------------------------------------------------------------------
                         slack                                  1.245                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.076ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].p2d/p_i/wfa/wtop_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - rxoutclk_1 rise@0.000ns)
  Data Path Delay:        0.672ns  (logic 0.049ns (7.292%)  route 0.623ns (92.708%))
  Logic Levels:           0  
  Clock Path Skew:        0.540ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.440ns
    Source Clock Delay      (SCD):    0.900ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.782ns (routing 0.222ns, distribution 0.560ns)
  Clock Net Delay (Destination): 1.275ns (routing 0.384ns, distribution 0.891ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        0.782     0.900                         niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/clk
    SLICE_X90Y224        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[6]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X90Y224        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.049     0.949 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[6]/Q
                         net (fo=5, routed)           0.623     1.572                         niop/bnk/genblk2[0].genblk1[1].p2d/p_i/wfa/wtop_reg[8]_0[6]
    SLICE_X90Y220        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/p_i/wfa/wtop_reg[6]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.275     1.440                         niop/bnk/genblk2[0].genblk1[1].p2d/p_i/wfa/txusrclk2
    SLICE_X90Y220        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/p_i/wfa/wtop_reg[6]/C
                         clock pessimism              0.000     1.440                           
    SLICE_X90Y220        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.056     1.496    AG_niop                niop/bnk/genblk2[0].genblk1[1].p2d/p_i/wfa/wtop_reg[6]
  -------------------------------------------------------------------
                         required time                         -1.496                           
                         arrival time                           1.572                           
  -------------------------------------------------------------------
                         slack                                  0.076                           





---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk_2
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :            0  Failing Endpoints,  Worst Slack        1.314ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.065ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.314ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vcnt_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/wrdx_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@3.200ns - rxoutclk_2 rise@0.000ns)
  Data Path Delay:        1.749ns  (logic 0.553ns (31.618%)  route 1.196ns (68.382%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.161ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.362ns = ( 5.562 - 3.200 ) 
    Source Clock Delay      (SCD):    2.523ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.126ns (routing 0.584ns, distribution 1.542ns)
  Clock Net Delay (Destination): 2.033ns (routing 0.567ns, distribution 1.466ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        2.126     2.523                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/clk
    SLICE_X92Y258        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vcnt_reg[13]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X92Y258        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     2.637 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vcnt_reg[13]/Q
                         net (fo=3, routed)           0.526     3.163                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vcnt_reg__0[13]
    SLICE_X94Y260        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.178     3.341 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/wrdx[2]_i_6__1/O
                         net (fo=1, routed)           0.430     3.771                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/wrdx[2]_i_6__1_n_0
    SLICE_X94Y259        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.073     3.844 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/wrdx[2]_i_3__1/O
                         net (fo=1, routed)           0.213     4.057                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/wrdx[2]_i_3__1_n_0
    SLICE_X95Y259        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.188     4.245 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/wrdx[2]_i_1__1/O
                         net (fo=1, routed)           0.027     4.272                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/p_1_out[2]
    SLICE_X95Y259        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/wrdx_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.033     5.562                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/txusrclk2
    SLICE_X95Y259        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/wrdx_reg[2]/C
                         clock pessimism              0.000     5.562                           
                         clock uncertainty           -0.035     5.527                           
    SLICE_X95Y259        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.059     5.586    AG_niop                niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/wrdx_reg[2]
  -------------------------------------------------------------------
                         required time                          5.586                           
                         arrival time                          -4.272                           
  -------------------------------------------------------------------
                         slack                                  1.314                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.065ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].p2d/p_i/wfa/wtop_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - rxoutclk_2 rise@0.000ns)
  Data Path Delay:        0.500ns  (logic 0.049ns (9.800%)  route 0.451ns (90.200%))
  Logic Levels:           0  
  Clock Path Skew:        0.379ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.452ns
    Source Clock Delay      (SCD):    1.073ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.955ns (routing 0.304ns, distribution 0.651ns)
  Clock Net Delay (Destination): 1.287ns (routing 0.384ns, distribution 0.903ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        0.955     1.073                         niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/clk
    SLICE_X91Y257        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[4]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y257        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.049     1.122 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[4]/Q
                         net (fo=5, routed)           0.451     1.573                         niop/bnk/genblk2[0].genblk1[2].p2d/p_i/wfa/wtop_reg[8]_0[4]
    SLICE_X91Y245        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/p_i/wfa/wtop_reg[4]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.287     1.452                         niop/bnk/genblk2[0].genblk1[2].p2d/p_i/wfa/txusrclk2
    SLICE_X91Y245        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/p_i/wfa/wtop_reg[4]/C
                         clock pessimism              0.000     1.452                           
    SLICE_X91Y245        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.056     1.508    AG_niop                niop/bnk/genblk2[0].genblk1[2].p2d/p_i/wfa/wtop_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.508                           
                         arrival time                           1.573                           
  -------------------------------------------------------------------
                         slack                                  0.065                           





---------------------------------------------------------------------------------------------------
From Clock:  rxoutclk_3
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :            0  Failing Endpoints,  Worst Slack        1.254ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.077ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.254ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vcnt_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/wrdx_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@3.200ns - rxoutclk_3 rise@0.000ns)
  Data Path Delay:        1.898ns  (logic 0.727ns (38.303%)  route 1.171ns (61.697%))
  Logic Levels:           3  (CARRY8=2 LUT3=1)
  Clock Path Skew:        -0.072ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.356ns = ( 5.556 - 3.200 ) 
    Source Clock Delay      (SCD):    2.428ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.031ns (routing 0.575ns, distribution 1.456ns)
  Clock Net Delay (Destination): 2.027ns (routing 0.567ns, distribution 1.460ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_3 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        2.031     2.428                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/clk
    SLICE_X91Y280        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vcnt_reg[2]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y280        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.113     2.541 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vcnt_reg[2]/Q
                         net (fo=7, routed)           0.534     3.075                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vcnt_reg[2]
    SLICE_X92Y281        CARRY8 (Prop_CARRY8_SLICEL_DI[1]_CO[7])
                                                      0.341     3.416 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/odif_carry/CO[7]
                         net (fo=1, routed)           0.027     3.443                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/odif_carry_n_0
    SLICE_X92Y282        CARRY8 (Prop_CARRY8_SLICEL_CI_O[4])
                                                      0.141     3.584 f  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/odif_carry__0/O[4]
                         net (fo=1, routed)           0.583     4.167                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/odif0_out[13]
    SLICE_X90Y282        LUT3 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.132     4.299 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/wrdx[2]_i_1__2/O
                         net (fo=1, routed)           0.027     4.326                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/p_1_out[2]
    SLICE_X90Y282        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/wrdx_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.027     5.556                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/txusrclk2
    SLICE_X90Y282        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/wrdx_reg[2]/C
                         clock pessimism              0.000     5.556                           
                         clock uncertainty           -0.035     5.521                           
    SLICE_X90Y282        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.059     5.580    AG_niop                niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/wrdx_reg[2]
  -------------------------------------------------------------------
                         required time                          5.580                           
                         arrival time                          -4.326                           
  -------------------------------------------------------------------
                         slack                                  1.254                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.077ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].p2d/p_i/wfa/wtop_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - rxoutclk_3 rise@0.000ns)
  Data Path Delay:        0.563ns  (logic 0.048ns (8.526%)  route 0.515ns (91.474%))
  Logic Levels:           0  
  Clock Path Skew:        0.431ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.440ns
    Source Clock Delay      (SCD):    1.009ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.891ns (routing 0.302ns, distribution 0.589ns)
  Clock Net Delay (Destination): 1.275ns (routing 0.384ns, distribution 0.891ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rxoutclk_3 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        0.891     1.009                         niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/clk
    SLICE_X91Y278        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[4]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y278        FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.048     1.057 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[4]/Q
                         net (fo=5, routed)           0.515     1.572                         niop/bnk/genblk2[0].genblk1[3].p2d/p_i/wfa/wtop_reg[8]_0[4]
    SLICE_X91Y275        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/p_i/wfa/wtop_reg[4]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.275     1.440                         niop/bnk/genblk2[0].genblk1[3].p2d/p_i/wfa/txusrclk2
    SLICE_X91Y275        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/p_i/wfa/wtop_reg[4]/C
                         clock pessimism              0.000     1.440                           
    SLICE_X91Y275        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.055     1.495    AG_niop                niop/bnk/genblk2[0].genblk1[3].p2d/p_i/wfa/wtop_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.495                           
                         arrival time                           1.572                           
  -------------------------------------------------------------------
                         slack                                  0.077                           





---------------------------------------------------------------------------------------------------
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  rxoutclk

Setup :            0  Failing Endpoints,  Worst Slack        0.582ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.084ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.582ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].p2d/s_ena_reg/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vcnt_reg[10]/R
                            (rising edge-triggered cell FDRE clocked by rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk rise@3.200ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        2.116ns  (logic 0.306ns (14.461%)  route 1.810ns (85.539%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.383ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.264ns = ( 5.464 - 3.200 ) 
    Source Clock Delay      (SCD):    2.647ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.250ns (routing 0.623ns, distribution 1.627ns)
  Clock Net Delay (Destination): 1.935ns (routing 0.508ns, distribution 1.427ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.250     2.647                         niop/bnk/genblk2[0].genblk1[0].p2d/txusrclk2
    SLICE_X85Y207        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/s_ena_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X85Y207        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.117     2.764 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/s_ena_reg/Q
                         net (fo=4, routed)           0.643     3.407                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/s_ena
    SLICE_X87Y197        LUT2 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.189     3.596 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vordx_i_2/O
                         net (fo=66, routed)          1.167     4.763                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/SR[0]
    SLICE_X90Y180        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vcnt_reg[10]/R
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.935     5.464                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/clk
    SLICE_X90Y180        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vcnt_reg[10]/C
                         clock pessimism              0.000     5.464                           
                         clock uncertainty           -0.035     5.429                           
    SLICE_X90Y180        FDRE (Setup_BFF_SLICEL_C_R)
                                                     -0.084     5.345    AG_niop                niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vcnt_reg[10]
  -------------------------------------------------------------------
                         required time                          5.345                           
                         arrival time                          -4.763                           
  -------------------------------------------------------------------
                         slack                                  0.582                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.084ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].nolabel_line376/ocnt_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].nolabel_line376/idifs_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.304ns  (logic 0.170ns (55.921%)  route 0.134ns (44.079%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        0.164ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.288ns
    Source Clock Delay      (SCD):    1.124ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.006ns (routing 0.339ns, distribution 0.667ns)
  Clock Net Delay (Destination): 1.123ns (routing 0.360ns, distribution 0.763ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.006     1.124                         niop/bnk/genblk2[0].genblk1[0].nolabel_line376/txusrclk2
    SLICE_X79Y162        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].nolabel_line376/ocnt_reg[5]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X79Y162        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.049     1.173 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].nolabel_line376/ocnt_reg[5]/Q
                         net (fo=4, routed)           0.084     1.257                         niop/bnk/genblk2[0].genblk1[0].nolabel_line376/ocnt_reg[5]
    SLICE_X79Y163        LUT3 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.064     1.321 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].nolabel_line376/odifs[2]_i_2__2/O
                         net (fo=2, routed)           0.038     1.359                         niop/bnk/genblk2[0].genblk1[0].nolabel_line376/odifs[2]_i_2__2_n_0
    SLICE_X79Y163        LUT5 (Prop_H5LUT_SLICEM_I4_O)
                                                      0.057     1.416 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].nolabel_line376/idifs[2]_i_1__2/O
                         net (fo=1, routed)           0.012     1.428                         niop/bnk/genblk2[0].genblk1[0].nolabel_line376/idifs0
    SLICE_X79Y163        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].nolabel_line376/idifs_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.123     1.288                         niop/bnk/genblk2[0].genblk1[0].nolabel_line376/clk
    SLICE_X79Y163        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].nolabel_line376/idifs_reg[2]/C
                         clock pessimism              0.000     1.288                           
    SLICE_X79Y163        FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.056     1.344    AG_niop                niop/bnk/genblk2[0].genblk1[0].nolabel_line376/idifs_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.344                           
                         arrival time                           1.428                           
  -------------------------------------------------------------------
                         slack                                  0.084                           





---------------------------------------------------------------------------------------------------
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  rxoutclk_1

Setup :            0  Failing Endpoints,  Worst Slack        0.664ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.288ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.664ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].srstx_reg/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].e2p/sval_reg/R
                            (rising edge-triggered cell FDRE clocked by rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_1 rise@3.200ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        1.571ns  (logic 0.114ns (7.257%)  route 1.457ns (92.743%))
  Logic Levels:           0  
  Clock Path Skew:        -0.846ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.819ns = ( 5.019 - 3.200 ) 
    Source Clock Delay      (SCD):    2.665ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.268ns (routing 0.623ns, distribution 1.645ns)
  Clock Net Delay (Destination): 1.490ns (routing 0.372ns, distribution 1.118ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.268     2.665                         niop/bnk/txusrclk2
    SLICE_X87Y221        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].srstx_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X87Y221        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     2.779 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].srstx_reg/Q
                         net (fo=25, routed)          1.457     4.236                         niop/bnk/genblk2[0].genblk1[1].e2p/rst
    SLICE_X89Y174        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].e2p/sval_reg/R
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_1 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.490     5.019                         niop/bnk/genblk2[0].genblk1[1].e2p/CLK
    SLICE_X89Y174        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].e2p/sval_reg/C
                         clock pessimism              0.000     5.019                           
                         clock uncertainty           -0.035     4.984                           
    SLICE_X89Y174        FDRE (Setup_DFF_SLICEL_C_R)
                                                     -0.084     4.900    AG_niop                niop/bnk/genblk2[0].genblk1[1].e2p/sval_reg
  -------------------------------------------------------------------
                         required time                          4.900                           
                         arrival time                          -4.236                           
  -------------------------------------------------------------------
                         slack                                  0.664                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.288ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].nolabel_line376/ocnt_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].nolabel_line376/idifs_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_1 rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.275ns  (logic 0.111ns (40.364%)  route 0.164ns (59.636%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.069ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.107ns
    Source Clock Delay      (SCD):    1.176ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.058ns (routing 0.339ns, distribution 0.719ns)
  Clock Net Delay (Destination): 0.942ns (routing 0.256ns, distribution 0.686ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.058     1.176                         niop/bnk/genblk2[0].genblk1[1].nolabel_line376/txusrclk2
    SLICE_X86Y198        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].nolabel_line376/ocnt_reg[6]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X86Y198        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.048     1.224 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].nolabel_line376/ocnt_reg[6]/Q
                         net (fo=5, routed)           0.152     1.376                         niop/bnk/genblk2[0].genblk1[1].nolabel_line376/ocnt_reg[6]
    SLICE_X86Y193        LUT5 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.063     1.439 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].nolabel_line376/idifs[2]_i_1__1/O
                         net (fo=1, routed)           0.012     1.451                         niop/bnk/genblk2[0].genblk1[1].nolabel_line376/idifs0
    SLICE_X86Y193        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].nolabel_line376/idifs_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        0.942     1.107                         niop/bnk/genblk2[0].genblk1[1].nolabel_line376/clk
    SLICE_X86Y193        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].nolabel_line376/idifs_reg[2]/C
                         clock pessimism              0.000     1.107                           
    SLICE_X86Y193        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.056     1.163    AG_niop                niop/bnk/genblk2[0].genblk1[1].nolabel_line376/idifs_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.163                           
                         arrival time                           1.451                           
  -------------------------------------------------------------------
                         slack                                  0.288                           





---------------------------------------------------------------------------------------------------
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  rxoutclk_2

Setup :            0  Failing Endpoints,  Worst Slack        0.641ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.199ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.641ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].p2d/xrst_reg/C
                            (rising edge-triggered cell FDSE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vcnt_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_2 rise@3.200ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        1.926ns  (logic 0.157ns (8.152%)  route 1.769ns (91.848%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.514ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.198ns = ( 5.398 - 3.200 ) 
    Source Clock Delay      (SCD):    2.712ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.315ns (routing 0.623ns, distribution 1.692ns)
  Clock Net Delay (Destination): 1.869ns (routing 0.527ns, distribution 1.342ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.315     2.712                         niop/bnk/genblk2[0].genblk1[2].p2d/txusrclk2
    SLICE_X95Y245        FDSE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/xrst_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X95Y245        FDSE (Prop_HFF2_SLICEL_C_Q)
                                                      0.117     2.829 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/xrst_reg/Q
                         net (fo=3, routed)           0.308     3.137                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/xrst
    SLICE_X95Y243        LUT2 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.040     3.177 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vordx_i_2__1/O
                         net (fo=66, routed)          1.461     4.638                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/SR[0]
    SLICE_X92Y257        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vcnt_reg[2]/R
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.869     5.398                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/clk
    SLICE_X92Y257        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vcnt_reg[2]/C
                         clock pessimism              0.000     5.398                           
                         clock uncertainty           -0.035     5.363                           
    SLICE_X92Y257        FDRE (Setup_BFF_SLICEL_C_R)
                                                     -0.084     5.279    AG_niop                niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vcnt_reg[2]
  -------------------------------------------------------------------
                         required time                          5.279                           
                         arrival time                          -4.638                           
  -------------------------------------------------------------------
                         slack                                  0.641                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.199ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].nolabel_line376/ocnt_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].nolabel_line376/idifs_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_2 rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.327ns  (logic 0.112ns (34.251%)  route 0.215ns (65.749%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.249ns
    Source Clock Delay      (SCD):    1.177ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.059ns (routing 0.339ns, distribution 0.720ns)
  Clock Net Delay (Destination): 1.084ns (routing 0.346ns, distribution 0.738ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.059     1.177                         niop/bnk/genblk2[0].genblk1[2].nolabel_line376/txusrclk2
    SLICE_X91Y209        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].nolabel_line376/ocnt_reg[7]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y209        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.049     1.226 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].nolabel_line376/ocnt_reg[7]/Q
                         net (fo=4, routed)           0.204     1.430                         niop/bnk/genblk2[0].genblk1[2].nolabel_line376/ocnt_reg[7]
    SLICE_X93Y211        LUT5 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.063     1.493 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].nolabel_line376/idifs[2]_i_1__0/O
                         net (fo=1, routed)           0.011     1.504                         niop/bnk/genblk2[0].genblk1[2].nolabel_line376/idifs0
    SLICE_X93Y211        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].nolabel_line376/idifs_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.084     1.249                         niop/bnk/genblk2[0].genblk1[2].nolabel_line376/clk
    SLICE_X93Y211        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].nolabel_line376/idifs_reg[2]/C
                         clock pessimism              0.000     1.249                           
    SLICE_X93Y211        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.056     1.305    AG_niop                niop/bnk/genblk2[0].genblk1[2].nolabel_line376/idifs_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.305                           
                         arrival time                           1.504                           
  -------------------------------------------------------------------
                         slack                                  0.199                           





---------------------------------------------------------------------------------------------------
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  rxoutclk_3

Setup :            0  Failing Endpoints,  Worst Slack        0.568ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.231ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.568ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].p2d/xrst_reg/C
                            (rising edge-triggered cell FDSE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vcnt_reg[10]/R
                            (rising edge-triggered cell FDRE clocked by rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_3
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_3 rise@3.200ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        1.927ns  (logic 0.233ns (12.091%)  route 1.694ns (87.909%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.586ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.121ns = ( 5.321 - 3.200 ) 
    Source Clock Delay      (SCD):    2.707ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.310ns (routing 0.623ns, distribution 1.687ns)
  Clock Net Delay (Destination): 1.792ns (routing 0.520ns, distribution 1.272ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.310     2.707                         niop/bnk/genblk2[0].genblk1[3].p2d/txusrclk2
    SLICE_X94Y265        FDSE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/xrst_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X94Y265        FDSE (Prop_HFF2_SLICEM_C_Q)
                                                      0.117     2.824 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/xrst_reg/Q
                         net (fo=3, routed)           0.318     3.142                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/xrst
    SLICE_X91Y262        LUT2 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.116     3.258 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vordx_i_2__2/O
                         net (fo=66, routed)          1.376     4.634                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/SR[0]
    SLICE_X91Y281        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vcnt_reg[10]/R
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_3 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.792     5.321                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/clk
    SLICE_X91Y281        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vcnt_reg[10]/C
                         clock pessimism              0.000     5.321                           
                         clock uncertainty           -0.035     5.286                           
    SLICE_X91Y281        FDRE (Setup_BFF_SLICEL_C_R)
                                                     -0.084     5.202    AG_niop                niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vcnt_reg[10]
  -------------------------------------------------------------------
                         required time                          5.202                           
                         arrival time                          -4.634                           
  -------------------------------------------------------------------
                         slack                                  0.568                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.231ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].nolabel_line376/ocnt_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].nolabel_line376/idifs_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             rxoutclk_3
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_3 rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.303ns  (logic 0.124ns (40.924%)  route 0.179ns (59.076%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.218ns
    Source Clock Delay      (SCD):    1.202ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.084ns (routing 0.339ns, distribution 0.745ns)
  Clock Net Delay (Destination): 1.053ns (routing 0.345ns, distribution 0.708ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.084     1.202                         niop/bnk/genblk2[0].genblk1[3].nolabel_line376/txusrclk2
    SLICE_X91Y228        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].nolabel_line376/ocnt_reg[7]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y228        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.048     1.250 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].nolabel_line376/ocnt_reg[7]/Q
                         net (fo=4, routed)           0.168     1.418                         niop/bnk/genblk2[0].genblk1[3].nolabel_line376/ocnt_reg[7]
    SLICE_X90Y228        LUT5 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.076     1.494 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].nolabel_line376/idifs[2]_i_1/O
                         net (fo=1, routed)           0.011     1.505                         niop/bnk/genblk2[0].genblk1[3].nolabel_line376/idifs0
    SLICE_X90Y228        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].nolabel_line376/idifs_reg[2]/D
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_3 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.053     1.218                         niop/bnk/genblk2[0].genblk1[3].nolabel_line376/clk
    SLICE_X90Y228        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].nolabel_line376/idifs_reg[2]/C
                         clock pessimism              0.000     1.218                           
    SLICE_X90Y228        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.056     1.274    AG_niop                niop/bnk/genblk2[0].genblk1[3].nolabel_line376/idifs_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.274                           
                         arrival time                           1.505                           
  -------------------------------------------------------------------
                         slack                                  0.231                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  GTHE3_CHANNEL_RXOUTCLK[0]
  To Clock:  GTHE3_CHANNEL_RXOUTCLK[0]

Setup :            0  Failing Endpoints,  Worst Slack        3.381ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.289ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.381ns  (required time - arrival time)
  Source:                 riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C
                            (rising edge-triggered cell FDCE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg/CLR
                            (recovery check against rising-edge clock GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.267ns  (GTHE3_CHANNEL_RXOUTCLK[0] rise@4.267ns - GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        0.703ns  (logic 0.114ns (16.216%)  route 0.589ns (83.784%))
  Logic Levels:           0  
  Clock Path Skew:        -0.065ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns = ( 6.608 - 4.267 ) 
    Source Clock Delay      (SCD):    2.672ns
    Clock Pessimism Removal (CPR):    0.266ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.275ns (routing 0.702ns, distribution 1.573ns)
  Clock Net Delay (Destination): 2.012ns (routing 0.637ns, distribution 1.375ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        2.275     2.672                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/CLK
    SLICE_X96Y67         FDCE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y67         FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     2.786 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q
                         net (fo=6, routed)           0.589     3.375                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_sync2_reg_0
    SLICE_X96Y79         FDCE                                         f  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      4.267     4.267 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     4.267 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     4.313                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.596 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        2.012     6.608                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/CLK
    SLICE_X96Y79         FDCE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg/C
                         clock pessimism              0.266     6.873                           
                         clock uncertainty           -0.035     6.838                           
    SLICE_X96Y79         FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                     -0.082     6.756    AG_riop                riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg
  -------------------------------------------------------------------
                         required time                          6.756                           
                         arrival time                          -3.375                           
  -------------------------------------------------------------------
                         slack                                  3.381                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.289ns  (arrival time - required time)
  Source:                 riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C
                            (rising edge-triggered cell FDCE clocked by GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_out_reg/CLR
                            (removal check against rising-edge clock GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns - GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        0.327ns  (logic 0.049ns (14.985%)  route 0.278ns (85.015%))
  Logic Levels:           0  
  Clock Path Skew:        0.033ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.380ns
    Source Clock Delay      (SCD):    1.155ns
    Clock Pessimism Removal (CPR):    0.192ns
  Clock Net Delay (Source):      1.037ns (routing 0.371ns, distribution 0.666ns)
  Clock Net Delay (Destination): 1.215ns (routing 0.422ns, distribution 0.793ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.037     1.155                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/CLK
    SLICE_X96Y67         FDCE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y67         FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.049     1.204 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Q
                         net (fo=6, routed)           0.278     1.482                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_sync2_reg_0
    SLICE_X96Y79         FDCE                                         f  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_out_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.215     1.380                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/CLK
    SLICE_X96Y79         FDCE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_out_reg/C
                         clock pessimism             -0.192     1.188                           
    SLICE_X96Y79         FDCE (Remov_EFF_SLICEL_C_CLR)
                                                      0.005     1.193    AG_riop                riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_rx_inst/gen_gtwiz_buffbypass_rx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_out_reg
  -------------------------------------------------------------------
                         required time                         -1.193                           
                         arrival time                           1.482                           
  -------------------------------------------------------------------
                         slack                                  0.289                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclkx
  To Clock:  GTHE3_CHANNEL_RXOUTCLK[0]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :            0  Failing Endpoints,  Worst Slack        1.493ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.493ns  (arrival time - required time)
  Source:                 dmac/rhb_reg/C
                            (rising edge-triggered cell FDSE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            hi/fab/vfa2/virdy_reg/CLR
                            (removal check against rising-edge clock GTHE3_CHANNEL_RXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (GTHE3_CHANNEL_RXOUTCLK[0] rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.229ns  (logic 0.048ns (20.961%)  route 0.181ns (79.039%))
  Logic Levels:           0  
  Clock Path Skew:        -1.416ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.301ns
    Source Clock Delay      (SCD):    2.717ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.864ns (routing 0.127ns, distribution 0.737ns)
  Clock Net Delay (Destination): 1.136ns (routing 0.422ns, distribution 0.714ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.864     2.717                         dmac/ioclk
    SLICE_X69Y149        FDSE                                         r  AG_dmac              dmac/rhb_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X69Y149        FDSE (Prop_HFF_SLICEM_C_Q)
                                                      0.048     2.765 f  AG_dmac              dmac/rhb_reg/Q
                         net (fo=19, routed)          0.181     2.946                         hi/fab/vfa2/hrios[0]
    SLICE_X71Y149        FDCE                                         f  AG_riop              hi/fab/vfa2/virdy_reg/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_RXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         riop/bnk1/rxclks
    BUFG_GT_X0Y21        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_riop              riop/bnk1/rxbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=1055, routed)        1.136     1.301                         hi/fab/vfa2/rclk1[0]
    SLICE_X71Y149        FDCE                                         r  AG_riop              hi/fab/vfa2/virdy_reg/C
                         clock pessimism              0.000     1.301                           
                         clock uncertainty            0.147     1.448                           
    SLICE_X71Y149        FDCE (Remov_EFF_SLICEM_C_CLR)
                                                      0.005     1.453    AG_riop                hi/fab/vfa2/virdy_reg
  -------------------------------------------------------------------
                         required time                         -1.453                           
                         arrival time                           2.946                           
  -------------------------------------------------------------------
                         slack                                  1.493                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  GTHE3_CHANNEL_TXOUTCLK[0]
  To Clock:  GTHE3_CHANNEL_TXOUTCLK[0]

Setup :            0  Failing Endpoints,  Worst Slack        3.537ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.202ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.537ns  (required time - arrival time)
  Source:                 riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg/C
                            (rising edge-triggered cell FDCE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg/CLR
                            (recovery check against rising-edge clock GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.267ns  (GTHE3_CHANNEL_TXOUTCLK[0] rise@4.267ns - GTHE3_CHANNEL_TXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        0.568ns  (logic 0.114ns (20.070%)  route 0.454ns (79.930%))
  Logic Levels:           0  
  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.368ns = ( 6.635 - 4.267 ) 
    Source Clock Delay      (SCD):    2.677ns
    Clock Pessimism Removal (CPR):    0.265ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.280ns (routing 0.707ns, distribution 1.573ns)
  Clock Net Delay (Destination): 2.039ns (routing 0.642ns, distribution 1.397ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         2.280     2.677                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg_2
    SLICE_X96Y83         FDCE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y83         FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     2.791 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q
                         net (fo=6, routed)           0.454     3.245                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg_1
    SLICE_X96Y84         FDCE                                         f  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      4.267     4.267 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     4.267 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     4.313                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.596 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         2.039     6.635                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg_0
    SLICE_X96Y84         FDCE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg/C
                         clock pessimism              0.265     6.899                           
                         clock uncertainty           -0.035     6.864                           
    SLICE_X96Y84         FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                     -0.082     6.782    AG_riop                riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg
  -------------------------------------------------------------------
                         required time                          6.782                           
                         arrival time                          -3.245                           
  -------------------------------------------------------------------
                         slack                                  3.537                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.202ns  (arrival time - required time)
  Source:                 riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg/C
                            (rising edge-triggered cell FDCE clocked by GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Destination:            riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_out_reg/CLR
                            (removal check against rising-edge clock GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (GTHE3_CHANNEL_TXOUTCLK[0] rise@0.000ns - GTHE3_CHANNEL_TXOUTCLK[0] rise@0.000ns)
  Data Path Delay:        0.258ns  (logic 0.049ns (18.992%)  route 0.209ns (81.008%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.399ns
    Source Clock Delay      (SCD):    1.156ns
    Clock Pessimism Removal (CPR):    0.192ns
  Clock Net Delay (Source):      1.038ns (routing 0.373ns, distribution 0.665ns)
  Clock Net Delay (Destination): 1.234ns (routing 0.423ns, distribution 0.811ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         1.038     1.156                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg_2
    SLICE_X96Y83         FDCE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y83         FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.049     1.205 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg/Q
                         net (fo=6, routed)           0.209     1.414                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg_1
    SLICE_X96Y84         FDCE                                         f  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_out_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         1.234     1.399                         riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_meta_reg_0
    SLICE_X96Y84         FDCE                                         r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_out_reg/C
                         clock pessimism             -0.192     1.207                           
    SLICE_X96Y84         FDCE (Remov_EFF_SLICEL_C_CLR)
                                                      0.005     1.212    AG_riop                riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_tx_buffer_bypass_internal.gen_single_instance.gtwiz_buffbypass_tx_inst/gen_gtwiz_buffbypass_tx_main.gen_auto_mode.reset_synchronizer_resetdone_inst/rst_in_out_reg
  -------------------------------------------------------------------
                         required time                         -1.212                           
                         arrival time                           1.414                           
  -------------------------------------------------------------------
                         slack                                  0.202                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclkx
  To Clock:  GTHE3_CHANNEL_TXOUTCLK[0]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :            0  Failing Endpoints,  Worst Slack        1.948ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.948ns  (arrival time - required time)
  Source:                 sc/rio_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            ho/fab/wfa0/vcnt_reg[0]/CLR
                            (removal check against rising-edge clock GTHE3_CHANNEL_TXOUTCLK[0]  {rise@0.000ns fall@2.133ns period=4.267ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (GTHE3_CHANNEL_TXOUTCLK[0] rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.603ns  (logic 0.048ns (7.960%)  route 0.555ns (92.040%))
  Logic Levels:           0  
  Clock Path Skew:        -1.497ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.314ns
    Source Clock Delay      (SCD):    2.811ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.958ns (routing 0.127ns, distribution 0.831ns)
  Clock Net Delay (Destination): 1.149ns (routing 0.423ns, distribution 0.726ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.958     2.811                         sc/ioclk
    SLICE_X88Y129        FDRE                                         r                       sc/rio_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X88Y129        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.048     2.859 f                       sc/rio_reg/Q
                         net (fo=187, routed)         0.555     3.414                         ho/fab/wfa0/AR[0]
    SLICE_X75Y140        FDCE                                         f  AG_riop              ho/fab/wfa0/vcnt_reg[0]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock GTHE3_CHANNEL_TXOUTCLK[0] rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y0   GTHE3_CHANNEL                0.000     0.000 r  AG_riop              riop/bnk1/gtinst/inst/gen_gtwizard_gthe3_top.gtrio_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         riop/bnk1/txclks
    BUFG_GT_X0Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_riop              riop/bnk1/txbufg/O
    X2Y1 (CLOCK_ROOT)    net (fo=633, routed)         1.149     1.314                         ho/fab/wfa0/rclk1__0[0]
    SLICE_X75Y140        FDCE                                         r  AG_riop              ho/fab/wfa0/vcnt_reg[0]/C
                         clock pessimism              0.000     1.314                           
                         clock uncertainty            0.147     1.461                           
    SLICE_X75Y140        FDCE (Remov_AFF2_SLICEM_C_CLR)
                                                      0.005     1.466    AG_riop                ho/fab/wfa0/vcnt_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.466                           
                         arrival time                           3.414                           
  -------------------------------------------------------------------
                         slack                                  1.948                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK

Setup :            0  Failing Endpoints,  Worst Slack       30.901ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.163ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             30.901ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {rise@0.000ns fall@16.500ns period=33.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {rise@0.000ns fall@16.500ns period=33.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            33.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
  Data Path Delay:        1.849ns  (logic 0.456ns (24.662%)  route 1.393ns (75.338%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.133ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.876ns = ( 38.876 - 33.000 ) 
    Source Clock Delay      (SCD):    7.113ns
    Clock Pessimism Removal (CPR):    1.104ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.415ns (routing 1.033ns, distribution 1.382ns)
  Clock Net Delay (Destination): 2.141ns (routing 0.947ns, distribution 1.194ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           4.615     4.615    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y106        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     4.698 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X0Y2 (CLOCK_ROOT)    net (fo=478, routed)         2.415     7.113    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X31Y135        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y135        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.114     7.227 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[4]/Q
                         net (fo=1, routed)           0.212     7.439    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[4]
    SLICE_X31Y135        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.188     7.627 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.223     7.850    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X32Y136        LUT4 (Prop_D5LUT_SLICEM_I3_O)
                                                      0.154     8.004 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.958     8.962    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X27Y144        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
                                                     33.000    33.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.660    36.660    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y106        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075    36.735 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X0Y2 (CLOCK_ROOT)    net (fo=478, routed)         2.141    38.876    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X27Y144        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/C
                         clock pessimism              1.104    39.980    
                         clock uncertainty           -0.035    39.945    
    SLICE_X27Y144        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.082    39.863    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]
  -------------------------------------------------------------------
                         required time                         39.863    
                         arrival time                          -8.962    
  -------------------------------------------------------------------
                         slack                                 30.901    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.163ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {rise@0.000ns fall@16.500ns period=33.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK  {rise@0.000ns fall@16.500ns period=33.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
  Data Path Delay:        0.220ns  (logic 0.049ns (22.273%)  route 0.171ns (77.727%))
  Logic Levels:           0  
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.459ns
    Source Clock Delay      (SCD):    3.465ns
    Clock Pessimism Removal (CPR):    0.942ns
  Clock Net Delay (Source):      1.100ns (routing 0.485ns, distribution 0.615ns)
  Clock Net Delay (Destination): 1.259ns (routing 0.538ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.338     2.338    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y106        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     2.365 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X0Y2 (CLOCK_ROOT)    net (fo=478, routed)         1.100     3.465    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X36Y162        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y162        FDPE (Prop_EFF_SLICEM_C_Q)
                                                      0.049     3.514 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.171     3.685    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X35Y162        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.169     3.169    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y106        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     3.200 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X0Y2 (CLOCK_ROOT)    net (fo=478, routed)         1.259     4.459    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X35Y162        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/C
                         clock pessimism             -0.942     3.517    
    SLICE_X35Y162        FDCE (Remov_GFF2_SLICEM_C_CLR)
                                                      0.005     3.522    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.522    
                         arrival time                           3.685    
  -------------------------------------------------------------------
                         slack                                  0.163    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclkf
  To Clock:  gclkf

Setup :            0  Failing Endpoints,  Worst Slack        1.665ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.186ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.665ns  (required time - arrival time)
  Source:                 core1/cor[2].p1.engi/rst_reg/C
                            (rising edge-triggered cell FDSE clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Destination:            core1/cor[2].p1.engi/sf/fifo/wfa/vcnt_reg[1]/CLR
                            (recovery check against rising-edge clock gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            6.000ns  (gclkf rise@6.000ns - gclkf rise@0.000ns)
  Data Path Delay:        3.715ns  (logic 0.114ns (3.069%)  route 3.601ns (96.931%))
  Logic Levels:           0  
  Clock Path Skew:        -0.469ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.893ns = ( 11.893 - 6.000 ) 
    Source Clock Delay      (SCD):    6.483ns
    Clock Pessimism Removal (CPR):    0.120ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.090ns (routing 1.079ns, distribution 2.011ns)
  Clock Net Delay (Destination): 2.450ns (routing 0.991ns, distribution 1.459ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.354     3.137                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.906 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.404     3.310                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.393 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      3.090     6.483                         core1/cor[2].p1.engi/gclkf[0]
    SLICE_X73Y255        FDSE                                         r  AG_cores             core1/cor[2].p1.engi/rst_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X73Y255        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.114     6.597 f  AG_cores             core1/cor[2].p1.engi/rst_reg/Q
                         net (fo=123, routed)         3.601    10.198                         core1/cor[2].p1.engi/sf/fifo/wfa/AR[0]
    SLICE_X40Y240        FDCE                                         f  AG_cores             core1/cor[2].p1.engi/sf/fifo/wfa/vcnt_reg[1]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkf rise edge)      6.000     6.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     6.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     6.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     6.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     6.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.128     8.687                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     9.022 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.346     9.368                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     9.443 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      2.450    11.893                         core1/cor[2].p1.engi/sf/fifo/wfa/gclkf[0]
    SLICE_X40Y240        FDCE                                         r  AG_cores             core1/cor[2].p1.engi/sf/fifo/wfa/vcnt_reg[1]/C
                         clock pessimism              0.120    12.014                           
                         clock uncertainty           -0.068    11.945                           
    SLICE_X40Y240        FDCE (Recov_BFF_SLICEM_C_CLR)
                                                     -0.082    11.863    AG_cores               core1/cor[2].p1.engi/sf/fifo/wfa/vcnt_reg[1]
  -------------------------------------------------------------------
                         required time                         11.863                           
                         arrival time                         -10.198                           
  -------------------------------------------------------------------
                         slack                                  1.665                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.186ns  (arrival time - required time)
  Source:                 core1/cor[4].p1.engi/rfp/s_ena_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Destination:            core1/cor[4].p1.engi/rfp/f_o/vfa/virdy_reg/CLR
                            (removal check against rising-edge clock gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclkf rise@0.000ns - gclkf rise@0.000ns)
  Data Path Delay:        0.316ns  (logic 0.048ns (15.190%)  route 0.268ns (84.810%))
  Logic Levels:           0  
  Clock Path Skew:        0.125ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.101ns
    Source Clock Delay      (SCD):    3.035ns
    Clock Pessimism Removal (CPR):    -0.059ns
  Clock Net Delay (Source):      1.205ns (routing 0.526ns, distribution 0.679ns)
  Clock Net Delay (Destination): 1.387ns (routing 0.583ns, distribution 0.804ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.078     1.380                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.650 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.153     1.803                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.830 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      1.205     3.035                         core1/cor[4].p1.engi/rfp/gclkf[0]
    SLICE_X33Y100        FDRE                                         r  AG_cores             core1/cor[4].p1.engi/rfp/s_ena_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X33Y100        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.048     3.083 r  AG_cores             core1/cor[4].p1.engi/rfp/s_ena_reg/Q
                         net (fo=26, routed)          0.268     3.351                         core1/cor[4].p1.engi/rfp/f_o/vfa/s_ena
    SLICE_X33Y121        FDCE                                         f  AG_cores             core1/cor[4].p1.engi/rfp/f_o/vfa/virdy_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.244     1.681                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.207     1.474 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.209     1.683                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.714 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      1.387     3.101                         core1/cor[4].p1.engi/rfp/f_o/vfa/gclkf[0]
    SLICE_X33Y121        FDCE                                         r  AG_cores             core1/cor[4].p1.engi/rfp/f_o/vfa/virdy_reg/C
                         clock pessimism              0.059     3.160                           
    SLICE_X33Y121        FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                      0.005     3.165    AG_cores               core1/cor[4].p1.engi/rfp/f_o/vfa/virdy_reg
  -------------------------------------------------------------------
                         required time                         -3.165                           
                         arrival time                           3.351                           
  -------------------------------------------------------------------
                         slack                                  0.186                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclks
  To Clock:  gclks

Setup :            0  Failing Endpoints,  Worst Slack        7.686ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.140ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.686ns  (required time - arrival time)
  Source:                 niop/sysreg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_meta_reg/PRE
                            (recovery check against rising-edge clock gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (gclks rise@10.000ns - gclks rise@0.000ns)
  Data Path Delay:        2.113ns  (logic 0.248ns (11.737%)  route 1.865ns (88.263%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.660ns = ( 15.660 - 10.000 ) 
    Source Clock Delay      (SCD):    5.847ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.061ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.212ns (routing 0.353ns, distribution 1.859ns)
  Clock Net Delay (Destination): 2.022ns (routing 0.326ns, distribution 1.696ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.212     5.847                         niop/gclks
    SLICE_X87Y155        FDRE                                         r  AG_niop              niop/sysreg_reg[2]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X87Y155        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     5.961 f  AG_niop              niop/sysreg_reg[2]/Q
                         net (fo=9, routed)           1.245     7.206                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_out_reg_0[0]
    SLICE_X97Y132        LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.134     7.340 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_meta_i_1__11/O
                         net (fo=5, routed)           0.620     7.960                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/p_1_in_0
    SLICE_X97Y121        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_meta_reg/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclks rise edge)     10.000    10.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r                       qclkp (IN)
                         net (fo=0)                   0.000    10.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230    10.230 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046    10.276                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283    10.559 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164    12.723                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.335    13.058 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.356    13.414                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.224    13.638 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.022    15.660                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/gclks
    SLICE_X97Y121        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_meta_reg/C
                         clock pessimism              0.129    15.789                           
                         clock uncertainty           -0.061    15.728                           
    SLICE_X97Y121        FDPE (Recov_DFF2_SLICEL_C_PRE)
                                                     -0.082    15.646    AG_niop                niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_meta_reg
  -------------------------------------------------------------------
                         required time                         15.646                           
                         arrival time                          -7.960                           
  -------------------------------------------------------------------
                         slack                                  7.686                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.140ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_rx_pll_and_datapath_int_reg/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_out_reg/PRE
                            (removal check against rising-edge clock gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclks rise@0.000ns - gclks rise@0.000ns)
  Data Path Delay:        0.219ns  (logic 0.048ns (21.918%)  route 0.171ns (78.082%))
  Logic Levels:           0  
  Clock Path Skew:        0.074ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.966ns
    Source Clock Delay      (SCD):    2.805ns
    Clock Pessimism Removal (CPR):    0.087ns
  Clock Net Delay (Source):      0.972ns (routing 0.135ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.148ns (routing 0.151ns, distribution 0.997ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.154     1.813                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.020     1.833 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        0.972     2.805                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gclks
    SLICE_X97Y131        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_rx_pll_and_datapath_int_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X97Y131        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.048     2.853 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_rx_pll_and_datapath_int_reg/Q
                         net (fo=7, routed)           0.171     3.024                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_meta_reg_0
    SLICE_X98Y131        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_out_reg/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.210     1.697                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.121     1.818 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        1.148     2.966                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/gclks
    SLICE_X98Y131        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_out_reg/C
                         clock pessimism             -0.087     2.880                           
    SLICE_X98Y131        FDPE (Remov_EFF_SLICEL_C_PRE)
                                                      0.005     2.885    AG_niop                niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_out_reg
  -------------------------------------------------------------------
                         required time                         -2.885                           
                         arrival time                           3.024                           
  -------------------------------------------------------------------
                         slack                                  0.140                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclkx
  To Clock:  gclks

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :            0  Failing Endpoints,  Worst Slack        0.473ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.473ns  (arrival time - required time)
  Source:                 sc/rprc_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE
                            (removal check against rising-edge clock gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclks rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        1.095ns  (logic 0.101ns (9.224%)  route 0.994ns (90.776%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.436ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.969ns
    Source Clock Delay      (SCD):    2.705ns
    Clock Pessimism Removal (CPR):    -0.172ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.852ns (routing 0.127ns, distribution 0.725ns)
  Clock Net Delay (Destination): 1.151ns (routing 0.151ns, distribution 1.000ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.852     2.705                         sc/ioclk
    SLICE_X59Y129        FDRE                                         r                       sc/rprc_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X59Y129        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.049     2.754 f                       sc/rprc_reg/Q
                         net (fo=122, routed)         0.736     3.490                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/riox
    SLICE_X97Y132        LUT4 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.052     3.542 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_i_1__10/O
                         net (fo=5, routed)           0.258     3.800                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/gtwiz_reset_tx_any
    SLICE_X97Y123        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.210     1.697                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.121     1.818 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        1.151     2.969                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/gclks
    SLICE_X97Y123        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/C
                         clock pessimism              0.172     3.141                           
                         clock uncertainty            0.181     3.323                           
    SLICE_X97Y123        FDPE (Remov_EFF_SLICEL_C_PRE)
                                                      0.005     3.328    AG_niop                niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg
  -------------------------------------------------------------------
                         required time                         -3.328                           
                         arrival time                           3.800                           
  -------------------------------------------------------------------
                         slack                                  0.473                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclkf
  To Clock:  gclkx

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :            0  Failing Endpoints,  Worst Slack        0.392ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.392ns  (arrival time - required time)
  Source:                 core1/cor[1].p1.engi/agc/s_ena_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkf  {rise@0.000ns fall@3.000ns period=6.000ns})
  Destination:            core1/cor[1].p1.engi/agc/f_i/vfa/vcnt_reg[5]/CLR
                            (removal check against rising-edge clock gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclkx rise@0.000ns - gclkf rise@0.000ns)
  Data Path Delay:        0.240ns  (logic 0.048ns (20.000%)  route 0.192ns (80.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.401ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.823ns
    Source Clock Delay      (SCD):    3.027ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.214ns
    Phase Error              (PE):    0.132ns
  Clock Net Delay (Source):      1.197ns (routing 0.526ns, distribution 0.671ns)
  Clock Net Delay (Destination): 1.096ns (routing 0.142ns, distribution 0.954ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkf rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.078     1.380                         sc/_clkp_n_0
    MMCME3_ADV_X1Y0      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.650 r                       sc/f_dcm/CLKOUT0
                         net (fo=1, routed)           0.153     1.803                         sc/lclkf
    BUFGCE_X1Y11         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.830 r                       sc/_clkf/O
    X1Y2 (CLOCK_ROOT)    net (fo=167354, routed)      1.197     3.027                         core1/cor[1].p1.engi/agc/gclkf[0]
    SLICE_X36Y209        FDRE                                         r  AG_cores             core1/cor[1].p1.engi/agc/s_ena_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X36Y209        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.048     3.075 r  AG_cores             core1/cor[1].p1.engi/agc/s_ena_reg/Q
                         net (fo=26, routed)          0.192     3.267                         core1/cor[1].p1.engi/agc/f_i/vfa/AR[0]
    SLICE_X37Y211        FDCE                                         f  AG_cores             core1/cor[1].p1.engi/agc/f_i/vfa/vcnt_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.209     1.696                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.727 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.096     2.823                         core1/cor[1].p1.engi/agc/f_i/vfa/ioclk
    SLICE_X37Y211        FDCE                                         r  AG_cores             core1/cor[1].p1.engi/agc/f_i/vfa/vcnt_reg[5]/C
                         clock pessimism             -0.197     2.626                           
                         clock uncertainty            0.244     2.871                           
    SLICE_X37Y211        FDCE (Remov_BFF_SLICEL_C_CLR)
                                                      0.005     2.876    AG_cores               core1/cor[1].p1.engi/agc/f_i/vfa/vcnt_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.876                           
                         arrival time                           3.267                           
  -------------------------------------------------------------------
                         slack                                  0.392                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclkx
  To Clock:  gclkx

Setup :            0  Failing Endpoints,  Worst Slack        1.026ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.133ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.026ns  (required time - arrival time)
  Source:                 core1/frst_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            core1/fi/vfa/virdy_reg/CLR
                            (recovery check against rising-edge clock gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.167ns  (gclkx rise@4.167ns - gclkx rise@0.000ns)
  Data Path Delay:        2.957ns  (logic 0.114ns (3.855%)  route 2.843ns (96.145%))
  Logic Levels:           0  
  Clock Path Skew:        -0.042ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.490ns = ( 9.657 - 4.167 ) 
    Source Clock Delay      (SCD):    5.519ns
    Clock Pessimism Removal (CPR):    -0.013ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.053ns (routing 0.335ns, distribution 1.718ns)
  Clock Net Delay (Destination): 1.985ns (routing 0.309ns, distribution 1.676ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.437     3.383                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.083     3.466 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        2.053     5.519                         core1/ioclk
    SLICE_X50Y116        FDRE                                         r  AG_cores             core1/frst_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X50Y116        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.114     5.633 f  AG_cores             core1/frst_reg/Q
                         net (fo=67, routed)          2.843     8.476                         core1/fi/vfa/SR[0]
    SLICE_X77Y187        FDCE                                         f  AG_cores             core1/fi/vfa/virdy_reg/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      4.167     4.167 r                       
    GTHE3_COMMON_X0Y2                                 0.000     4.167 r                       qclkp (IN)
                         net (fo=0)                   0.000     4.167                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230     4.397 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046     4.443                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.726 r                       sc/_clkp/O
                         net (fo=5, routed)           2.164     6.890                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.335     7.225 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.372     7.597                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.075     7.672 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.985     9.657                         core1/fi/vfa/ioclk
    SLICE_X77Y187        FDCE                                         r  AG_cores             core1/fi/vfa/virdy_reg/C
                         clock pessimism             -0.013     9.644                           
                         clock uncertainty           -0.060     9.584                           
    SLICE_X77Y187        FDCE (Recov_BFF2_SLICEL_C_CLR)
                                                     -0.082     9.502    AG_cores               core1/fi/vfa/virdy_reg
  -------------------------------------------------------------------
                         required time                          9.502                           
                         arrival time                          -8.476                           
  -------------------------------------------------------------------
                         slack                                  1.026                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.133ns  (arrival time - required time)
  Source:                 dmac/rha_reg/C
                            (rising edge-triggered cell FDSE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            hi/fab/wfa1/vcnt_reg[2]/CLR
                            (removal check against rising-edge clock gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (gclkx rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.229ns  (logic 0.049ns (21.397%)  route 0.180ns (78.603%))
  Logic Levels:           0  
  Clock Path Skew:        0.091ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.761ns
    Source Clock Delay      (SCD):    2.710ns
    Clock Pessimism Removal (CPR):    -0.040ns
  Clock Net Delay (Source):      0.857ns (routing 0.127ns, distribution 0.730ns)
  Clock Net Delay (Destination): 1.034ns (routing 0.142ns, distribution 0.892ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.857     2.710                         dmac/ioclk
    SLICE_X68Y152        FDSE                                         r  AG_dmac              dmac/rha_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X68Y152        FDSE (Prop_DFF2_SLICEL_C_Q)
                                                      0.049     2.759 f  AG_dmac              dmac/rha_reg/Q
                         net (fo=19, routed)          0.180     2.939                         hi/fab/wfa1/hrios[0]
    SLICE_X70Y151        FDCE                                         f  AG_riop              hi/fab/wfa1/vcnt_reg[2]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257     1.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                     -0.207     1.487 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.209     1.696                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.031     1.727 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        1.034     2.761                         hi/fab/wfa1/ioclk
    SLICE_X70Y151        FDCE                                         r  AG_riop              hi/fab/wfa1/vcnt_reg[2]/C
                         clock pessimism              0.040     2.801                           
    SLICE_X70Y151        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                      0.005     2.806    AG_riop                hi/fab/wfa1/vcnt_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.806                           
                         arrival time                           2.939                           
  -------------------------------------------------------------------
                         slack                                  0.133                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclkx
  To Clock:  gclky

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :            0  Failing Endpoints,  Worst Slack        0.721ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.721ns  (arrival time - required time)
  Source:                 ppc/srwx_reg/C
                            (falling edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            ppc/swrx__reg/CLR
                            (removal check against rising-edge clock gclky  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            -0.417ns  (gclky rise@10.000ns - gclkx fall@10.417ns)
  Data Path Delay:        0.378ns  (logic 0.048ns (12.698%)  route 0.330ns (87.302%))
  Logic Levels:           0  
  Clock Path Skew:        -0.113ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.417ns = ( 12.417 - 10.000 ) 
    Source Clock Delay      (SCD):    2.702ns = ( 13.119 - 10.417 ) 
    Clock Pessimism Removal (CPR):    -0.172ns
  Clock Uncertainty:      0.181ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.849ns (routing 0.127ns, distribution 0.722ns)
  Clock Net Delay (Destination): 0.599ns (routing 0.008ns, distribution 0.591ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx fall edge)     10.417    10.417 f                       
    GTHE3_COMMON_X0Y2                                 0.000    10.417 f                       qclkp (IN)
                         net (fo=0)                   0.000    10.417                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184    10.601 f                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018    10.619                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100    10.719 f                       sc/_clkp/O
                         net (fo=5, routed)           1.087    11.806                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270    12.076 f                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167    12.243                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027    12.270 f                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.849    13.119                         ppc/ioclk
    SLICE_X59Y139        FDRE                                         r  AG_dmac/AG_ppc       ppc/srwx_reg/C  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X59Y139        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.048    13.167 f  AG_dmac/AG_ppc       ppc/srwx_reg/Q
                         net (fo=2, routed)           0.330    13.497                         ppc/srwx
    SLICE_X57Y136        FDCE                                         f  AG_dmac/AG_ppc       ppc/swrx__reg/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gclky rise edge)     10.000    10.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r                       qclkp (IN)
                         net (fo=0)                   0.000    10.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272    10.272 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035    10.307                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130    10.437 r                       sc/_clkp/O
                         net (fo=5, routed)           1.257    11.694                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.207    11.487 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.210    11.697                         sc/lclky
    BUFGCE_DIV_X1Y9      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.121    11.818 r                       sc/_clky/O
    X2Y2 (CLOCK_ROOT)    net (fo=449, routed)         0.599    12.417                         ppc/bclk
    SLICE_X57Y136        FDCE                                         r  AG_dmac/AG_ppc       ppc/swrx__reg/C
                         clock pessimism              0.172    12.589                           
                         clock uncertainty            0.181    12.771                           
    SLICE_X57Y136        FDCE (Remov_DFF2_SLICEM_C_CLR)
                                                      0.005    12.776    AG_dmac/AG_ppc         ppc/swrx__reg
  -------------------------------------------------------------------
                         required time                        -12.776                           
                         arrival time                          13.497                           
  -------------------------------------------------------------------
                         slack                                  0.721                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclkx
  To Clock:  genblk1[0].user_clk_1

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :            0  Failing Endpoints,  Worst Slack        1.653ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.653ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].frst_reg/C
                            (rising edge-triggered cell FDSE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            nvmp/genblk1[0].xiow/wfa/vcnt_reg[0]/CLR
                            (removal check against rising-edge clock genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (genblk1[0].user_clk_1 rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.191ns  (logic 0.049ns (25.654%)  route 0.142ns (74.346%))
  Logic Levels:           0  
  Clock Path Skew:        -1.614ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.189ns
    Source Clock Delay      (SCD):    2.803ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.950ns (routing 0.127ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.024ns (routing 0.348ns, distribution 0.676ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.950     2.803                         nvmp/ioclk
    SLICE_X86Y73         FDSE                                         r  AG_nvmp              nvmp/genblk1[0].frst_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X86Y73         FDSE (Prop_EFF_SLICEL_C_Q)
                                                      0.049     2.852 f  AG_nvmp              nvmp/genblk1[0].frst_reg/Q
                         net (fo=42, routed)          0.142     2.994                         nvmp/genblk1[0].xiow/wfa/AR[0]
    SLICE_X87Y73         FDCE                                         f  AG_nvmp              nvmp/genblk1[0].xiow/wfa/vcnt_reg[0]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.035     0.035                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.024     1.189                         nvmp/genblk1[0].xiow/wfa/CLK_USERCLK
    SLICE_X87Y73         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].xiow/wfa/vcnt_reg[0]/C
                         clock pessimism              0.000     1.189                           
                         clock uncertainty            0.147     1.336                           
    SLICE_X87Y73         FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                      0.005     1.341    AG_nvmp                nvmp/genblk1[0].xiow/wfa/vcnt_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.341                           
                         arrival time                           2.994                           
  -------------------------------------------------------------------
                         slack                                  1.653                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  genblk1[0].user_clk_1
  To Clock:  genblk1[0].user_clk_1

Setup :            0  Failing Endpoints,  Worst Slack        0.896ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.250ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.896ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/tph_tbl_inst/reg_cfg_tph_stt_read_data_valid_o_reg/CLR
                            (recovery check against rising-edge clock genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            4.000ns  (genblk1[0].user_clk_1 rise@4.000ns - genblk1[0].user_clk_1 rise@0.000ns)
  Data Path Delay:        2.873ns  (logic 0.234ns (8.145%)  route 2.639ns (91.855%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.988ns = ( 5.988 - 4.000 ) 
    Source Clock Delay      (SCD):    2.271ns
    Clock Pessimism Removal (CPR):    0.169ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.874ns (routing 0.606ns, distribution 1.268ns)
  Clock Net Delay (Destination): 1.659ns (routing 0.548ns, distribution 1.111ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.082     0.082                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.874     2.271                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/CLK_USERCLK
    SLICE_X94Y52         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[2]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X94Y52         FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.114     2.385 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[2]/Q
                         net (fo=6, routed)           0.088     2.473                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg_n_0_[2]
    SLICE_X94Y52         LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.120     2.593 f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/pipe_stages_1.pipe_tx_eqcontrol_q[1]_i_1/O
                         net (fo=505, routed)         2.551     5.144                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/tph_tbl_inst/reg_cfg_tph_stt_read_enable_i_reg_0
    SLICE_X87Y16         FDCE                                         f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/tph_tbl_inst/reg_cfg_tph_stt_read_data_valid_o_reg/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock genblk1[0].user_clk_1 rise edge)
                                                      4.000     4.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     4.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.046     4.046                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     4.329 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         1.659     5.988                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/tph_tbl_inst/CLK_USERCLK
    SLICE_X87Y16         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/tph_tbl_inst/reg_cfg_tph_stt_read_data_valid_o_reg/C
                         clock pessimism              0.169     6.157                           
                         clock uncertainty           -0.035     6.122                           
    SLICE_X87Y16         FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                     -0.082     6.040    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/tph_tbl_inst/reg_cfg_tph_stt_read_data_valid_o_reg
  -------------------------------------------------------------------
                         required time                          6.040                           
                         arrival time                          -5.144                           
  -------------------------------------------------------------------
                         slack                                  0.896                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.250ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_cold_reset_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[0]/CLR
                            (removal check against rising-edge clock genblk1[0].user_clk_1  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (genblk1[0].user_clk_1 rise@0.000ns - genblk1[0].user_clk_1 rise@0.000ns)
  Data Path Delay:        0.345ns  (logic 0.048ns (13.913%)  route 0.297ns (86.087%))
  Logic Levels:           0  
  Clock Path Skew:        0.090ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.149ns
    Source Clock Delay      (SCD):    0.970ns
    Clock Pessimism Removal (CPR):    0.089ns
  Clock Net Delay (Source):      0.852ns (routing 0.306ns, distribution 0.546ns)
  Clock Net Delay (Destination): 0.984ns (routing 0.348ns, distribution 0.636ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.018     0.018                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         0.852     0.970                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/CLK_USERCLK
    SLICE_X96Y65         FDSE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_cold_reset_reg[1]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y65         FDSE (Prop_EFF2_SLICEL_C_Q)
                                                      0.048     1.018 f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_cold_reset_reg[1]/Q
                         net (fo=3, routed)           0.297     1.315                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/p_0_in
    SLICE_X94Y52         FDCE                                         f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[0]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock genblk1[0].user_clk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y4   GTHE3_CHANNEL                0.000     0.000 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/gt_wizard.gtwizard_top_i/pcif_0_gt_i/inst/gen_gtwizard_gthe3_top.pcif_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=5, routed)           0.035     0.035                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK_IN
    BUFG_GT_X0Y39        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_clk_i/bufg_gt_userclk/O
    X3Y0 (CLOCK_ROOT)    net (fo=727, routed)         0.984     1.149                         nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/CLK_USERCLK
    SLICE_X94Y52         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[0]/C
                         clock pessimism             -0.089     1.060                           
    SLICE_X94Y52         FDCE (Remov_HFF2_SLICEM_C_CLR)
                                                      0.005     1.065    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/pcie3_uscale_top_inst/init_ctrl_inst/reg_state_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.065                           
                         arrival time                           1.315                           
  -------------------------------------------------------------------
                         slack                                  0.250                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclks
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :            0  Failing Endpoints,  Worst Slack        1.433ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.433ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_tx_done_int_reg/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg/CLR
                            (removal check against rising-edge clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - gclks rise@0.000ns)
  Data Path Delay:        0.209ns  (logic 0.048ns (22.966%)  route 0.161ns (77.033%))
  Logic Levels:           0  
  Clock Path Skew:        -1.377ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.423ns
    Source Clock Delay      (SCD):    2.800ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.967ns (routing 0.135ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.258ns (routing 0.384ns, distribution 0.874ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.154     1.813                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.020     1.833 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        0.967     2.800                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gclks
    SLICE_X96Y142        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_tx_done_int_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y142        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.048     2.848 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/gtwiz_reset_tx_done_int_reg/Q
                         net (fo=8, routed)           0.161     3.009                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg_0
    SLICE_X93Y142        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.258     1.423                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/txusrclk2
    SLICE_X93Y142        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg/C
                         clock pessimism              0.000     1.423                           
                         clock uncertainty            0.149     1.572                           
    SLICE_X93Y142        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                      0.005     1.577    AG_niop                niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_tx_done_inst/rst_in_out_reg
  -------------------------------------------------------------------
                         required time                         -1.577                           
                         arrival time                           3.009                           
  -------------------------------------------------------------------
                         slack                                  1.433                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclkx
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :            0  Failing Endpoints,  Worst Slack        1.736ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.736ns  (arrival time - required time)
  Source:                 niop/rstx_reg/C
                            (rising edge-triggered cell FDRE clocked by gclkx  {rise@0.000ns fall@2.083ns period=4.167ns})
  Destination:            niop/bnk/ofifo/vfa/virdy_reg/CLR
                            (removal check against rising-edge clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - gclkx rise@0.000ns)
  Data Path Delay:        0.506ns  (logic 0.049ns (9.684%)  route 0.457ns (90.316%))
  Logic Levels:           0  
  Clock Path Skew:        -1.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.368ns
    Source Clock Delay      (SCD):    2.750ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.147ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.097ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.897ns (routing 0.127ns, distribution 0.770ns)
  Clock Net Delay (Destination): 1.203ns (routing 0.384ns, distribution 0.819ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclkx rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT0)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT0
                         net (fo=1, routed)           0.167     1.826                         sc/lclkx
    BUFGCE_X1Y60         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.853 r                       sc/_clkx/O
    X2Y2 (CLOCK_ROOT)    net (fo=5566, routed)        0.897     2.750                         niop/ioclk
    SLICE_X81Y151        FDRE                                         r  AG_niop              niop/rstx_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X81Y151        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.049     2.799 f  AG_niop              niop/rstx_reg/Q
                         net (fo=40, routed)          0.457     3.256                         niop/bnk/ofifo/vfa/SR[0]
    SLICE_X85Y132        FDCE                                         f  AG_niop              niop/bnk/ofifo/vfa/virdy_reg/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.203     1.368                         niop/bnk/ofifo/vfa/txusrclk2
    SLICE_X85Y132        FDCE                                         r  AG_niop              niop/bnk/ofifo/vfa/virdy_reg/C
                         clock pessimism              0.000     1.368                           
                         clock uncertainty            0.147     1.515                           
    SLICE_X85Y132        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                      0.005     1.520    AG_niop                niop/bnk/ofifo/vfa/virdy_reg
  -------------------------------------------------------------------
                         required time                         -1.520                           
                         arrival time                           3.256                           
  -------------------------------------------------------------------
                         slack                                  1.736                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :            0  Failing Endpoints,  Worst Slack        0.250ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.264ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.250ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].p2d/noOut_reg/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].p2d/f_o/wfa/vcnt_reg[1]/CLR
                            (recovery check against rising-edge clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.200ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@3.200ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        2.536ns  (logic 0.113ns (4.456%)  route 2.423ns (95.544%))
  Logic Levels:           0  
  Clock Path Skew:        -0.297ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.311ns = ( 5.511 - 3.200 ) 
    Source Clock Delay      (SCD):    2.732ns
    Clock Pessimism Removal (CPR):    0.124ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.335ns (routing 0.623ns, distribution 1.712ns)
  Clock Net Delay (Destination): 1.982ns (routing 0.567ns, distribution 1.415ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.335     2.732                         niop/bnk/genblk2[0].genblk1[2].p2d/txusrclk2
    SLICE_X99Y253        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/noOut_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X99Y253        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.113     2.845 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/noOut_reg/Q
                         net (fo=24, routed)          2.423     5.268                         niop/bnk/genblk2[0].genblk1[2].p2d/f_o/wfa/vordx_reg_1
    SLICE_X86Y148        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_o/wfa/vcnt_reg[1]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.982     5.511                         niop/bnk/genblk2[0].genblk1[2].p2d/f_o/wfa/txusrclk2
    SLICE_X86Y148        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_o/wfa/vcnt_reg[1]/C
                         clock pessimism              0.124     5.635                           
                         clock uncertainty           -0.035     5.600                           
    SLICE_X86Y148        FDCE (Recov_HFF_SLICEL_C_CLR)
                                                     -0.082     5.518    AG_niop                niop/bnk/genblk2[0].genblk1[2].p2d/f_o/wfa/vcnt_reg[1]
  -------------------------------------------------------------------
                         required time                          5.518                           
                         arrival time                          -5.268                           
  -------------------------------------------------------------------
                         slack                                  0.250                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.264ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].p2d/s_ena_reg/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].p2d/p_o/vfa/virdy_reg/CLR
                            (removal check against rising-edge clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.351ns  (logic 0.093ns (26.496%)  route 0.258ns (73.504%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.082ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.464ns
    Source Clock Delay      (SCD):    1.225ns
    Clock Pessimism Removal (CPR):    0.157ns
  Clock Net Delay (Source):      1.107ns (routing 0.339ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.299ns (routing 0.384ns, distribution 0.915ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.107     1.225                         niop/bnk/genblk2[0].genblk1[2].p2d/txusrclk2
    SLICE_X95Y244        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/s_ena_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X95Y244        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.048     1.273 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/s_ena_reg/Q
                         net (fo=4, routed)           0.074     1.347                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/s_ena
    SLICE_X95Y243        LUT2 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.045     1.392 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vordx_i_2__1/O
                         net (fo=66, routed)          0.184     1.576                         niop/bnk/genblk2[0].genblk1[2].p2d/p_o/vfa/virdy_reg_0
    SLICE_X91Y243        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/p_o/vfa/virdy_reg/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.299     1.464                         niop/bnk/genblk2[0].genblk1[2].p2d/p_o/vfa/txusrclk2
    SLICE_X91Y243        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/p_o/vfa/virdy_reg/C
                         clock pessimism             -0.157     1.307                           
    SLICE_X91Y243        FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                      0.005     1.312    AG_niop                niop/bnk/genblk2[0].genblk1[2].p2d/p_o/vfa/virdy_reg
  -------------------------------------------------------------------
                         required time                         -1.312                           
                         arrival time                           1.576                           
  -------------------------------------------------------------------
                         slack                                  0.264                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  rclkp
  To Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2

Setup :            0  Failing Endpoints,  Worst Slack        1.663ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.067ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.663ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_tx_sync_i/data_out_reg/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/sync1_r_reg[1]/PRE
                            (recovery check against rising-edge clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.200ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@3.200ns - rclkp rise@0.000ns)
  Data Path Delay:        1.210ns  (logic 0.114ns (9.421%)  route 1.096ns (90.579%))
  Logic Levels:           0  
  Clock Path Skew:        -0.209ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.314ns = ( 5.514 - 3.200 ) 
    Source Clock Delay      (SCD):    2.523ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.768ns (routing 0.489ns, distribution 1.279ns)
  Clock Net Delay (Destination): 1.985ns (routing 0.567ns, distribution 1.418ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.358     0.358 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.082     0.440                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.755 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.768     2.523                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_tx_sync_i/sync1_r_reg[4]_0
    SLICE_X86Y129        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_tx_sync_i/data_out_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X86Y129        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     2.637 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_tx_sync_i/data_out_reg/Q
                         net (fo=5, routed)           1.096     3.733                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/AS[0]
    SLICE_X85Y129        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/sync1_r_reg[1]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.985     5.514                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/txusrclk2
    SLICE_X85Y129        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/sync1_r_reg[1]/C
                         clock pessimism              0.000     5.514                           
                         clock uncertainty           -0.035     5.479                           
    SLICE_X85Y129        FDPE (Recov_AFF2_SLICEL_C_PRE)
                                                     -0.082     5.397    AG_niop                niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/sync1_r_reg[1]
  -------------------------------------------------------------------
                         required time                          5.397                           
                         arrival time                          -3.733                           
  -------------------------------------------------------------------
                         slack                                  1.663                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.067ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_tx_sync_i/data_out_reg/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/sync1_r_reg[0]/PRE
                            (removal check against rising-edge clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns - rclkp rise@0.000ns)
  Data Path Delay:        0.453ns  (logic 0.049ns (10.817%)  route 0.404ns (89.183%))
  Logic Levels:           0  
  Clock Path Skew:        0.381ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.407ns
    Source Clock Delay      (SCD):    1.026ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.747ns (routing 0.252ns, distribution 0.495ns)
  Clock Net Delay (Destination): 1.242ns (routing 0.384ns, distribution 0.858ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.161     0.161 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.018     0.179                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.279 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.747     1.026                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_tx_sync_i/sync1_r_reg[4]_0
    SLICE_X92Y151        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_tx_sync_i/data_out_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X92Y151        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.049     1.075 f  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_tx_sync_i/data_out_reg/Q
                         net (fo=5, routed)           0.404     1.479                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/AS[0]
    SLICE_X92Y150        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/sync1_r_reg[0]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.242     1.407                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/txusrclk2
    SLICE_X92Y150        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     1.407                           
    SLICE_X92Y150        FDPE (Remov_HFF2_SLICEL_C_PRE)
                                                      0.005     1.412    AG_niop                niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/txreset_txusrclk2_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.412                           
                         arrival time                           1.479                           
  -------------------------------------------------------------------
                         slack                                  0.067                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  lclks
  To Clock:  lclks

Setup :            0  Failing Endpoints,  Worst Slack        7.213ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.605ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.213ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/C
                            (rising edge-triggered cell FDPE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/PRE
                            (recovery check against rising-edge clock lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (lclks rise@10.000ns - lclks rise@0.000ns)
  Data Path Delay:        2.514ns  (logic 0.187ns (7.438%)  route 2.327ns (92.562%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.124ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.680ns = ( 14.680 - 10.000 ) 
    Source Clock Delay      (SCD):    4.790ns
    Clock Pessimism Removal (CPR):    -0.014ns
  Clock Uncertainty:      0.067ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.114ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.957ns, distribution 1.437ns)
  Clock Net Delay (Destination): 2.164ns (routing 0.870ns, distribution 1.294ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock lclks rise edge)      0.000     0.000 r  
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r  qclkp (IN)
                         net (fo=0)                   0.000     0.000    sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r  sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468    sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r  sc/_clkp/O
    X2Y1 (CLOCK_ROOT)    net (fo=5, routed)           2.394     3.177    sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                     -0.231     2.946 r  sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         1.844     4.790    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X34Y162        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y162        FDPE (Prop_HFF2_SLICEL_C_Q)
                                                      0.117     4.907 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/Q
                         net (fo=3, routed)           1.409     6.316    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst/in0[0]
    SLICE_X34Y162        LUT2 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.070     6.386 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst/ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1/O
                         net (fo=3, routed)           0.918     7.304    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb
    SLICE_X33Y160        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock lclks rise edge)     10.000    10.000 r  
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r  qclkp (IN)
                         net (fo=0)                   0.000    10.000    sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.230    10.230 r  sc/mgtq/ODIV2
                         net (fo=2, routed)           0.046    10.276    sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283    10.559 r  sc/_clkp/O
    X2Y1 (CLOCK_ROOT)    net (fo=5, routed)           2.164    12.723    sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                      0.335    13.058 r  sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         1.622    14.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X33Y160        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/C
                         clock pessimism             -0.014    14.666    
                         clock uncertainty           -0.067    14.599    
    SLICE_X33Y160        FDPE (Recov_AFF_SLICEL_C_PRE)
                                                     -0.082    14.517    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         14.517    
                         arrival time                          -7.304    
  -------------------------------------------------------------------
                         slack                                  7.213    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.605ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
                            (rising edge-triggered cell FDPE clocked by lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
                            (removal check against rising-edge clock lclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (lclks rise@0.000ns - lclks rise@0.000ns)
  Data Path Delay:        0.691ns  (logic 0.048ns (6.946%)  route 0.643ns (93.054%))
  Logic Levels:           0  
  Clock Path Skew:        0.081ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.402ns
    Source Clock Delay      (SCD):    2.431ns
    Clock Pessimism Removal (CPR):    -0.110ns
  Clock Net Delay (Source):      1.087ns (routing 0.504ns, distribution 0.583ns)
  Clock Net Delay (Destination): 1.257ns (routing 0.566ns, distribution 0.691ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock lclks rise edge)      0.000     0.000 r  
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r  qclkp (IN)
                         net (fo=0)                   0.000     0.000    sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r  sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202    sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r  sc/_clkp/O
    X2Y1 (CLOCK_ROOT)    net (fo=5, routed)           1.087     1.389    sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                      0.270     1.659 r  sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         0.772     2.431    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X35Y159        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y159        FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.048     2.479 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/Q
                         net (fo=1, routed)           0.643     3.122    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2
    SLICE_X34Y163        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock lclks rise edge)      0.000     0.000 r  
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r  qclkp (IN)
                         net (fo=0)                   0.000     0.000    sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.272     0.272 r  sc/mgtq/ODIV2
                         net (fo=2, routed)           0.035     0.307    sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.437 r  sc/_clkp/O
    X2Y1 (CLOCK_ROOT)    net (fo=5, routed)           1.257     1.694    sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT2)
                                                     -0.207     1.487 r  sc/o_dcm/CLKOUT2
                         net (fo=569, routed)         0.915     2.402    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X34Y163        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C
                         clock pessimism              0.110     2.513    
    SLICE_X34Y163        FDPE (Remov_HFF2_SLICEL_C_PRE)
                                                      0.005     2.518    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         -2.518    
                         arrival time                           3.122    
  -------------------------------------------------------------------
                         slack                                  0.605    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gclks
  To Clock:  pclkp

Setup :            0  Failing Endpoints,  Worst Slack        5.416ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.520ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             5.416ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].rstn_reg/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg[1]/CLR
                            (recovery check against rising-edge clock pclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (pclkp rise@10.000ns - gclks rise@0.000ns)
  Data Path Delay:        0.848ns  (logic 0.114ns (13.443%)  route 0.734ns (86.557%))
  Logic Levels:           0  
  Clock Path Skew:        -3.506ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.379ns = ( 12.379 - 10.000 ) 
    Source Clock Delay      (SCD):    5.885ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.250ns (routing 0.353ns, distribution 1.897ns)
  Clock Net Delay (Destination): 1.824ns (routing 0.687ns, distribution 1.137ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.386     0.386 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.082     0.468                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.783 r                       sc/_clkp/O
                         net (fo=5, routed)           2.394     3.177                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                     -0.231     2.946 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.407     3.353                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.282     3.635 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        2.250     5.885                         nvmp/gclks
    SLICE_X88Y70         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].rstn_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X88Y70         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     5.999 r  AG_nvmp              nvmp/genblk1[0].rstn_reg/Q
                         net (fo=18, routed)          0.734     6.733                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/genblk1[0].rstn
    SLICE_X91Y67         FDCE                                         f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pclkp rise edge)     10.000    10.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r                       pclkp (IN)
                         net (fo=0)                   0.000    10.000                         sc/pclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.226    10.226 r                       sc/mgtp/ODIV2
                         net (fo=2, routed)           0.046    10.272                         nvmp/genblk1[0].pcif_i/inst/sys_clk
    BUFG_GT_X0Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283    10.555 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/O
    X3Y1 (CLOCK_ROOT)    net (fo=143, routed)         1.824    12.379                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/sys_clk_bufg
    SLICE_X91Y67         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg[1]/C
                         clock pessimism              0.000    12.379                           
                         clock uncertainty           -0.149    12.231                           
    SLICE_X91Y67         FDCE (Recov_AFF2_SLICEL_C_CLR)
                                                     -0.082    12.149    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg[1]
  -------------------------------------------------------------------
                         required time                         12.149                           
                         arrival time                          -6.733                           
  -------------------------------------------------------------------
                         slack                                  5.416                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.520ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].rstn_reg/C
                            (rising edge-triggered cell FDRE clocked by gclks  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg[0]/CLR
                            (removal check against rising-edge clock pclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclkp rise@0.000ns - gclks rise@0.000ns)
  Data Path Delay:        0.404ns  (logic 0.049ns (12.129%)  route 0.355ns (87.871%))
  Logic Levels:           0  
  Clock Path Skew:        -1.269ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.544ns
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.980ns (routing 0.135ns, distribution 0.845ns)
  Clock Net Delay (Destination): 1.108ns (routing 0.441ns, distribution 0.667ns)
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gclks rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       qclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/qclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS1_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.184     0.184 r                       sc/mgtq/ODIV2
                         net (fo=2, routed)           0.018     0.202                         sc/mgtq_n_1
    BUFG_GT_X0Y53        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.302 r                       sc/_clkp/O
                         net (fo=5, routed)           1.087     1.389                         sc/_clkp_n_0
    MMCME3_ADV_X1Y2      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT3)
                                                      0.270     1.659 r                       sc/o_dcm/CLKOUT3
                         net (fo=2, routed)           0.154     1.813                         sc/lclky
    BUFGCE_DIV_X1Y8      BUFGCE_DIV (Prop_BUFGCE_DIV_I_O)
                                                      0.020     1.833 r                       sc/_clks/O
    X2Y2 (CLOCK_ROOT)    net (fo=1985, routed)        0.980     2.813                         nvmp/gclks
    SLICE_X88Y70         FDRE                                         r  AG_nvmp              nvmp/genblk1[0].rstn_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X88Y70         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.049     2.862 r  AG_nvmp              nvmp/genblk1[0].rstn_reg/Q
                         net (fo=18, routed)          0.355     3.217                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/genblk1[0].rstn
    SLICE_X91Y67         FDCE                                         f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       pclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/pclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.271     0.271 r                       sc/mgtp/ODIV2
                         net (fo=2, routed)           0.035     0.306                         nvmp/genblk1[0].pcif_i/inst/sys_clk
    BUFG_GT_X0Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.436 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/O
    X3Y1 (CLOCK_ROOT)    net (fo=143, routed)         1.108     1.544                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/sys_clk_bufg
    SLICE_X91Y67         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg[0]/C
                         clock pessimism              0.000     1.544                           
                         clock uncertainty            0.149     1.693                           
    SLICE_X91Y67         FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                      0.005     1.698    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.698                           
                         arrival time                           3.217                           
  -------------------------------------------------------------------
                         slack                                  1.520                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  pclkp
  To Clock:  pclkp

Setup :            0  Failing Endpoints,  Worst Slack        8.894ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.255ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             8.894ns  (required time - arrival time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg_reg/C
                            (rising edge-triggered cell FDCE clocked by pclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/FSM_onehot_fsm_reg[2]/CLR
                            (recovery check against rising-edge clock pclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (pclkp rise@10.000ns - pclkp rise@0.000ns)
  Data Path Delay:        0.866ns  (logic 0.114ns (13.164%)  route 0.752ns (86.836%))
  Logic Levels:           0  
  Clock Path Skew:        -0.122ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.381ns = ( 12.381 - 10.000 ) 
    Source Clock Delay      (SCD):    2.841ns
    Clock Pessimism Removal (CPR):    0.338ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.063ns (routing 0.759ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.826ns (routing 0.687ns, distribution 1.139ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock pclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       pclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/pclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.381     0.381 r                       sc/mgtp/ODIV2
                         net (fo=2, routed)           0.082     0.463                         nvmp/genblk1[0].pcif_i/inst/sys_clk
    BUFG_GT_X0Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.778 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/O
    X3Y1 (CLOCK_ROOT)    net (fo=143, routed)         2.063     2.841                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/sys_clk_bufg
    SLICE_X91Y67         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y67         FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     2.955 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg_reg/Q
                         net (fo=28, routed)          0.752     3.707                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/userrdy_reg_0
    SLICE_X100Y70        FDCE                                         f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/FSM_onehot_fsm_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pclkp rise edge)     10.000    10.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000    10.000 r                       pclkp (IN)
                         net (fo=0)                   0.000    10.000                         sc/pclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.226    10.226 r                       sc/mgtp/ODIV2
                         net (fo=2, routed)           0.046    10.272                         nvmp/genblk1[0].pcif_i/inst/sys_clk
    BUFG_GT_X0Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283    10.555 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/O
    X3Y1 (CLOCK_ROOT)    net (fo=143, routed)         1.826    12.381                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/sys_clk_bufg
    SLICE_X100Y70        FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/FSM_onehot_fsm_reg[2]/C
                         clock pessimism              0.338    12.719                           
                         clock uncertainty           -0.035    12.684                           
    SLICE_X100Y70        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.082    12.602    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/FSM_onehot_fsm_reg[2]
  -------------------------------------------------------------------
                         required time                         12.602                           
                         arrival time                          -3.707                           
  -------------------------------------------------------------------
                         slack                                  8.894                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.255ns  (arrival time - required time)
  Source:                 nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg_reg/C
                            (rising edge-triggered cell FDCE clocked by pclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/FSM_onehot_fsm_reg[5]/CLR
                            (removal check against rising-edge clock pclkp  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (pclkp rise@0.000ns - pclkp rise@0.000ns)
  Data Path Delay:        0.335ns  (logic 0.049ns (14.627%)  route 0.286ns (85.373%))
  Logic Levels:           0  
  Clock Path Skew:        0.075ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.542ns
    Source Clock Delay      (SCD):    1.237ns
    Clock Pessimism Removal (CPR):    0.229ns
  Clock Net Delay (Source):      0.936ns (routing 0.390ns, distribution 0.546ns)
  Clock Net Delay (Destination): 1.106ns (routing 0.441ns, distribution 0.665ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock pclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       pclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/pclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.183     0.183 r                       sc/mgtp/ODIV2
                         net (fo=2, routed)           0.018     0.201                         nvmp/genblk1[0].pcif_i/inst/sys_clk
    BUFG_GT_X0Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.301 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/O
    X3Y1 (CLOCK_ROOT)    net (fo=143, routed)         0.936     1.237                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/sys_clk_bufg
    SLICE_X91Y67         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y67         FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.049     1.286 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg_reg/Q
                         net (fo=28, routed)          0.286     1.572                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/userrdy_reg_0
    SLICE_X99Y69         FDCE                                         f  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/FSM_onehot_fsm_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    ----------------------------------------

                         (clock pclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y2                                 0.000     0.000 r                       pclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/pclkp
    GTHE3_COMMON_X0Y2    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.271     0.271 r                       sc/mgtp/ODIV2
                         net (fo=2, routed)           0.035     0.306                         nvmp/genblk1[0].pcif_i/inst/sys_clk
    BUFG_GT_X0Y54        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.436 r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/bufg_gt_sysclk/O
    X3Y1 (CLOCK_ROOT)    net (fo=143, routed)         1.106     1.542                         nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/sys_clk_bufg
    SLICE_X99Y69         FDCE                                         r  AG_nvmp              nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/FSM_onehot_fsm_reg[5]/C
                         clock pessimism             -0.229     1.313                           
    SLICE_X99Y69         FDCE (Remov_BFF_SLICEL_C_CLR)
                                                      0.005     1.318    AG_nvmp                nvmp/genblk1[0].pcif_i/inst/gt_top_i/phy_rst_i/FSM_onehot_fsm_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.318                           
                         arrival time                           1.572                           
  -------------------------------------------------------------------
                         slack                                  0.255                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  rclkp
  To Clock:  rclkp

Setup :            0  Failing Endpoints,  Worst Slack        4.864ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.137ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.864ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/data_out_reg/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/sync1_r_reg[1]/PRE
                            (recovery check against rising-edge clock rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            6.400ns  (rclkp rise@6.400ns - rclkp rise@0.000ns)
  Data Path Delay:        1.270ns  (logic 0.307ns (24.173%)  route 0.963ns (75.827%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.149ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.057ns = ( 8.457 - 6.400 ) 
    Source Clock Delay      (SCD):    2.519ns
    Clock Pessimism Removal (CPR):    0.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.764ns (routing 0.489ns, distribution 1.275ns)
  Clock Net Delay (Destination): 1.524ns (routing 0.441ns, distribution 1.083ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.358     0.358 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.082     0.440                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.755 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.764     2.519                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/CLK
    SLICE_X87Y145        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/data_out_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X87Y145        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     2.633 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gt0_rxresetdone_i_sync_i/data_out_reg/Q
                         net (fo=3, routed)           0.550     3.183                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_areset_sync_i/D[0]
    SLICE_X92Y145        LUT3 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.193     3.376 f  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_areset_sync_i/sync1_r[4]_i_1__2/O
                         net (fo=5, routed)           0.413     3.789                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/sync1_r_reg[4]_0[0]
    SLICE_X93Y146        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/sync1_r_reg[1]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      6.400     6.400 r                       
    GTHE3_COMMON_X0Y1                                 0.000     6.400 r                       rclkp (IN)
                         net (fo=0)                   0.000     6.400                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.204     6.604 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.046     6.650                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     6.933 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.524     8.457                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/data_out_reg_0
    SLICE_X93Y146        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/sync1_r_reg[1]/C
                         clock pessimism              0.314     8.771                           
                         clock uncertainty           -0.035     8.735                           
    SLICE_X93Y146        FDPE (Recov_AFF2_SLICEL_C_PRE)
                                                     -0.082     8.653    AG_niop                niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/sync1_r_reg[1]
  -------------------------------------------------------------------
                         required time                          8.653                           
                         arrival time                          -3.789                           
  -------------------------------------------------------------------
                         slack                                  4.864                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.137ns  (arrival time - required time)
  Source:                 niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/reset_pulse_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gtrxreset_coreclk_sync_i/sync1_r_reg[0]/PRE
                            (removal check against rising-edge clock rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (rclkp rise@0.000ns - rclkp rise@0.000ns)
  Data Path Delay:        0.225ns  (logic 0.049ns (21.778%)  route 0.176ns (78.222%))
  Logic Levels:           0  
  Clock Path Skew:        0.083ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.334ns
    Source Clock Delay      (SCD):    1.036ns
    Clock Pessimism Removal (CPR):    0.216ns
  Clock Net Delay (Source):      0.757ns (routing 0.252ns, distribution 0.505ns)
  Clock Net Delay (Destination): 0.921ns (routing 0.289ns, distribution 0.632ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.161     0.161 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.018     0.179                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.279 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.757     1.036                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/CLK
    SLICE_X95Y146        FDRE                                         r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/reset_pulse_reg[0]/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X95Y146        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.049     1.085 f  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/reset_pulse_reg[0]/Q
                         net (fo=40, routed)          0.176     1.261                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gtrxreset_coreclk_sync_i/sync1_r_reg[4]_0[0]
    SLICE_X96Y146        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gtrxreset_coreclk_sync_i/sync1_r_reg[0]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.248     0.248 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.035     0.283                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.413 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.921     1.334                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gtrxreset_coreclk_sync_i/CLK
    SLICE_X96Y146        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gtrxreset_coreclk_sync_i/sync1_r_reg[0]/C
                         clock pessimism             -0.216     1.118                           
    SLICE_X96Y146        FDPE (Remov_HFF2_SLICEL_C_PRE)
                                                      0.005     1.123    AG_niop                niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/gtrxreset_coreclk_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.123                           
                         arrival time                           1.261                           
  -------------------------------------------------------------------
                         slack                                  0.137                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  rxoutclk

Setup :            0  Failing Endpoints,  Worst Slack        1.085ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.205ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.085ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].p2d/s_ena_reg/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[0]/CLR
                            (recovery check against rising-edge clock rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk rise@3.200ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        1.566ns  (logic 0.306ns (19.540%)  route 1.260ns (80.460%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.215ns = ( 5.415 - 3.200 ) 
    Source Clock Delay      (SCD):    2.647ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.250ns (routing 0.623ns, distribution 1.627ns)
  Clock Net Delay (Destination): 1.886ns (routing 0.508ns, distribution 1.378ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.250     2.647                         niop/bnk/genblk2[0].genblk1[0].p2d/txusrclk2
    SLICE_X85Y207        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/s_ena_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X85Y207        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.117     2.764 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/s_ena_reg/Q
                         net (fo=4, routed)           0.643     3.407                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/s_ena
    SLICE_X87Y197        LUT2 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.189     3.596 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vordx_i_2/O
                         net (fo=66, routed)          0.617     4.213                         niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[0]_0
    SLICE_X83Y199        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[0]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.886     5.415                         niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/clk
    SLICE_X83Y199        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[0]/C
                         clock pessimism              0.000     5.415                           
                         clock uncertainty           -0.035     5.380                           
    SLICE_X83Y199        FDCE (Recov_FFF2_SLICEL_C_CLR)
                                                     -0.082     5.298    AG_niop                niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[0]
  -------------------------------------------------------------------
                         required time                          5.298                           
                         arrival time                          -4.213                           
  -------------------------------------------------------------------
                         slack                                  1.085                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.205ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].p2d/xrst_reg/C
                            (rising edge-triggered cell FDSE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[6]/CLR
                            (removal check against rising-edge clock rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.372ns  (logic 0.101ns (27.151%)  route 0.271ns (72.849%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.162ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.336ns
    Source Clock Delay      (SCD):    1.174ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.056ns (routing 0.339ns, distribution 0.717ns)
  Clock Net Delay (Destination): 1.171ns (routing 0.360ns, distribution 0.811ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.056     1.174                         niop/bnk/genblk2[0].genblk1[0].p2d/txusrclk2
    SLICE_X87Y197        FDSE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/xrst_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X87Y197        FDSE (Prop_CFF2_SLICEL_C_Q)
                                                      0.048     1.222 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/xrst_reg/Q
                         net (fo=3, routed)           0.043     1.265                         niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/xrst
    SLICE_X87Y197        LUT2 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.053     1.318 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/f_i/bif/vordx_i_2/O
                         net (fo=66, routed)          0.228     1.546                         niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[0]_0
    SLICE_X84Y199        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[6]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.171     1.336                         niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/clk
    SLICE_X84Y199        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[6]/C
                         clock pessimism              0.000     1.336                           
    SLICE_X84Y199        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                      0.005     1.341    AG_niop                niop/bnk/genblk2[0].genblk1[0].p2d/p_i/vfa/vcnt_reg[6]
  -------------------------------------------------------------------
                         required time                         -1.341                           
                         arrival time                           1.546                           
  -------------------------------------------------------------------
                         slack                                  0.205                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  rclkp
  To Clock:  rxoutclk

Setup :            0  Failing Endpoints,  Worst Slack        1.818ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.086ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.818ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]/PRE
                            (recovery check against rising-edge clock rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk rise@3.200ns - rclkp rise@0.000ns)
  Data Path Delay:        1.010ns  (logic 0.114ns (11.287%)  route 0.896ns (88.713%))
  Logic Levels:           0  
  Clock Path Skew:        -0.254ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.255ns = ( 5.455 - 3.200 ) 
    Source Clock Delay      (SCD):    2.509ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.754ns (routing 0.489ns, distribution 1.265ns)
  Clock Net Delay (Destination): 1.926ns (routing 0.508ns, distribution 1.418ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.358     0.358 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.082     0.440                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.755 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.754     2.509                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/data_out_reg
    SLICE_X93Y139        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X93Y139        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.114     2.623 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/Q
                         net (fo=6, routed)           0.896     3.519                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/AS[0]
    SLICE_X94Y134        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.926     5.455                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/CLK
    SLICE_X94Y134        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]/C
                         clock pessimism              0.000     5.455                           
                         clock uncertainty           -0.035     5.420                           
    SLICE_X94Y134        FDPE (Recov_AFF2_SLICEM_C_PRE)
                                                     -0.082     5.338    AG_niop                niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]
  -------------------------------------------------------------------
                         required time                          5.338                           
                         arrival time                          -3.519                           
  -------------------------------------------------------------------
                         slack                                  1.818                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.086ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_rising_reg__0/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[0]/PRE
                            (removal check against rising-edge clock rxoutclk  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk rise@0.000ns - rclkp rise@0.000ns)
  Data Path Delay:        0.393ns  (logic 0.049ns (12.468%)  route 0.344ns (87.532%))
  Logic Levels:           0  
  Clock Path Skew:        0.302ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.355ns
    Source Clock Delay      (SCD):    1.053ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.774ns (routing 0.252ns, distribution 0.522ns)
  Clock Net Delay (Destination): 1.190ns (routing 0.360ns, distribution 0.830ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.161     0.161 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.018     0.179                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.279 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.774     1.053                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/data_out_reg
    SLICE_X100Y133       FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_rising_reg__0/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X100Y133       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.049     1.102 f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_rising_reg__0/Q
                         net (fo=6, routed)           0.344     1.446                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_rising_rxusrclk2_sync_i/AS[0]
    SLICE_X98Y133        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[0]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y61        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.190     1.355                         niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_rising_rxusrclk2_sync_i/CLK
    SLICE_X98Y133        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     1.355                           
    SLICE_X98Y133        FDPE (Remov_HFF2_SLICEL_C_PRE)
                                                      0.005     1.360    AG_niop                niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_unpull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.360                           
                         arrival time                           1.446                           
  -------------------------------------------------------------------
                         slack                                  0.086                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  rxoutclk_1

Setup :            0  Failing Endpoints,  Worst Slack        0.625ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.714ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.625ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].p2d/s_ena_reg/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[3]/CLR
                            (recovery check against rising-edge clock rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_1 rise@3.200ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        1.595ns  (logic 0.306ns (19.185%)  route 1.289ns (80.815%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.863ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.853ns = ( 5.053 - 3.200 ) 
    Source Clock Delay      (SCD):    2.716ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.319ns (routing 0.623ns, distribution 1.696ns)
  Clock Net Delay (Destination): 1.524ns (routing 0.372ns, distribution 1.152ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.319     2.716                         niop/bnk/genblk2[0].genblk1[1].p2d/txusrclk2
    SLICE_X90Y220        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/s_ena_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X90Y220        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.117     2.833 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/s_ena_reg/Q
                         net (fo=4, routed)           0.294     3.127                         niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/s_ena
    SLICE_X93Y220        LUT2 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.189     3.316 f  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/vordx_i_2__0/O
                         net (fo=66, routed)          0.995     4.311                         niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[0]_0
    SLICE_X90Y224        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[3]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_1 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.524     5.053                         niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/clk
    SLICE_X90Y224        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[3]/C
                         clock pessimism              0.000     5.053                           
                         clock uncertainty           -0.035     5.018                           
    SLICE_X90Y224        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.082     4.936    AG_niop                niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[3]
  -------------------------------------------------------------------
                         required time                          4.936                           
                         arrival time                          -4.311                           
  -------------------------------------------------------------------
                         slack                                  0.625                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.714ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].p2d/xrst_reg/C
                            (rising edge-triggered cell FDSE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[0]/CLR
                            (removal check against rising-edge clock rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_1 rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.616ns  (logic 0.064ns (10.390%)  route 0.552ns (89.610%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.103ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.103ns
    Source Clock Delay      (SCD):    1.206ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.088ns (routing 0.339ns, distribution 0.749ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.256ns, distribution 0.682ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.088     1.206                         niop/bnk/genblk2[0].genblk1[1].p2d/txusrclk2
    SLICE_X93Y222        FDSE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/xrst_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X93Y222        FDSE (Prop_DFF2_SLICEL_C_Q)
                                                      0.049     1.255 f  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/xrst_reg/Q
                         net (fo=3, routed)           0.073     1.328                         niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/xrst
    SLICE_X93Y220        LUT2 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.015     1.343 f  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/f_i/bif/vordx_i_2__0/O
                         net (fo=66, routed)          0.479     1.822                         niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[0]_0
    SLICE_X90Y224        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[0]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        0.938     1.103                         niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/clk
    SLICE_X90Y224        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[0]/C
                         clock pessimism              0.000     1.103                           
    SLICE_X90Y224        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                      0.005     1.108    AG_niop                niop/bnk/genblk2[0].genblk1[1].p2d/p_i/vfa/vcnt_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.108                           
                         arrival time                           1.822                           
  -------------------------------------------------------------------
                         slack                                  0.714                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  rclkp
  To Clock:  rxoutclk_1

Setup :            0  Failing Endpoints,  Worst Slack        1.662ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.286ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.662ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/data_out_reg/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/sync1_r_reg[1]/PRE
                            (recovery check against rising-edge clock rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_1 rise@3.200ns - rclkp rise@0.000ns)
  Data Path Delay:        0.733ns  (logic 0.114ns (15.553%)  route 0.619ns (84.447%))
  Logic Levels:           0  
  Clock Path Skew:        -0.687ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.805ns = ( 5.005 - 3.200 ) 
    Source Clock Delay      (SCD):    2.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.737ns (routing 0.489ns, distribution 1.248ns)
  Clock Net Delay (Destination): 1.476ns (routing 0.372ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.358     0.358 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.082     0.440                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.755 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.737     2.492                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/data_out_reg_0
    SLICE_X91Y149        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/data_out_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y149        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.114     2.606 f  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/data_out_reg/Q
                         net (fo=5, routed)           0.619     3.225                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/AS[0]
    SLICE_X90Y148        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/sync1_r_reg[1]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_1 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        1.476     5.005                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/CLK
    SLICE_X90Y148        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/sync1_r_reg[1]/C
                         clock pessimism              0.000     5.005                           
                         clock uncertainty           -0.035     4.970                           
    SLICE_X90Y148        FDPE (Recov_AFF2_SLICEL_C_PRE)
                                                     -0.082     4.888    AG_niop                niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/sync1_r_reg[1]
  -------------------------------------------------------------------
                         required time                          4.888                           
                         arrival time                          -3.225                           
  -------------------------------------------------------------------
                         slack                                  1.662                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.286ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[0]/PRE
                            (removal check against rising-edge clock rxoutclk_1  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_1 rise@0.000ns - rclkp rise@0.000ns)
  Data Path Delay:        0.286ns  (logic 0.049ns (17.133%)  route 0.237ns (82.867%))
  Logic Levels:           0  
  Clock Path Skew:        -0.005ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.031ns
    Source Clock Delay      (SCD):    1.036ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.757ns (routing 0.252ns, distribution 0.505ns)
  Clock Net Delay (Destination): 0.866ns (routing 0.256ns, distribution 0.610ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.161     0.161 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.018     0.179                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.279 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.757     1.036                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/data_out_reg
    SLICE_X97Y148        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X97Y148        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.049     1.085 f  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/Q
                         net (fo=6, routed)           0.237     1.322                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/AS[0]
    SLICE_X100Y150       FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[0]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_1 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y9   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y70        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=1051, routed)        0.866     1.031                         niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/CLK
    SLICE_X100Y150       FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     1.031                           
    SLICE_X100Y150       FDPE (Remov_HFF2_SLICEM_C_PRE)
                                                      0.005     1.036    AG_niop                niop/bnk/genblk2[0].genblk1[1].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.036                           
                         arrival time                           1.322                           
  -------------------------------------------------------------------
                         slack                                  0.286                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  rxoutclk_2

Setup :            0  Failing Endpoints,  Worst Slack        0.646ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.782ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.646ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].p2d/xrst_reg/C
                            (rising edge-triggered cell FDSE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[0]/CLR
                            (recovery check against rising-edge clock rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_2 rise@3.200ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        1.920ns  (logic 0.157ns (8.177%)  route 1.763ns (91.823%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.517ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.195ns = ( 5.395 - 3.200 ) 
    Source Clock Delay      (SCD):    2.712ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.315ns (routing 0.623ns, distribution 1.692ns)
  Clock Net Delay (Destination): 1.866ns (routing 0.527ns, distribution 1.339ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.315     2.712                         niop/bnk/genblk2[0].genblk1[2].p2d/txusrclk2
    SLICE_X95Y245        FDSE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/xrst_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X95Y245        FDSE (Prop_HFF2_SLICEL_C_Q)
                                                      0.117     2.829 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/xrst_reg/Q
                         net (fo=3, routed)           0.308     3.137                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/xrst
    SLICE_X95Y243        LUT2 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.040     3.177 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vordx_i_2__1/O
                         net (fo=66, routed)          1.455     4.632                         niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[0]_0
    SLICE_X91Y257        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[0]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.866     5.395                         niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/clk
    SLICE_X91Y257        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[0]/C
                         clock pessimism              0.000     5.395                           
                         clock uncertainty           -0.035     5.360                           
    SLICE_X91Y257        FDCE (Recov_CFF2_SLICEL_C_CLR)
                                                     -0.082     5.278    AG_niop                niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[0]
  -------------------------------------------------------------------
                         required time                          5.278                           
                         arrival time                          -4.632                           
  -------------------------------------------------------------------
                         slack                                  0.646                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.782ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].p2d/s_ena_reg/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[1]/CLR
                            (removal check against rising-edge clock rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_2 rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.871ns  (logic 0.093ns (10.677%)  route 0.778ns (89.323%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.084ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.309ns
    Source Clock Delay      (SCD):    1.225ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.107ns (routing 0.339ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.144ns (routing 0.346ns, distribution 0.798ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.107     1.225                         niop/bnk/genblk2[0].genblk1[2].p2d/txusrclk2
    SLICE_X95Y244        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/s_ena_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X95Y244        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.048     1.273 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/s_ena_reg/Q
                         net (fo=4, routed)           0.074     1.347                         niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/s_ena
    SLICE_X95Y243        LUT2 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.045     1.392 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/f_i/bif/vordx_i_2__1/O
                         net (fo=66, routed)          0.704     2.096                         niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[0]_0
    SLICE_X93Y258        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[1]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.144     1.309                         niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/clk
    SLICE_X93Y258        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[1]/C
                         clock pessimism              0.000     1.309                           
    SLICE_X93Y258        FDCE (Remov_DFF_SLICEL_C_CLR)
                                                      0.005     1.314    AG_niop                niop/bnk/genblk2[0].genblk1[2].p2d/p_i/vfa/vcnt_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.314                           
                         arrival time                           2.096                           
  -------------------------------------------------------------------
                         slack                                  0.782                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  rclkp
  To Clock:  rxoutclk_2

Setup :            0  Failing Endpoints,  Worst Slack        1.937ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.055ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.937ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]/PRE
                            (recovery check against rising-edge clock rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_2 rise@3.200ns - rclkp rise@0.000ns)
  Data Path Delay:        0.791ns  (logic 0.114ns (14.412%)  route 0.677ns (85.588%))
  Logic Levels:           0  
  Clock Path Skew:        -0.354ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.176ns = ( 5.376 - 3.200 ) 
    Source Clock Delay      (SCD):    2.530ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.775ns (routing 0.489ns, distribution 1.286ns)
  Clock Net Delay (Destination): 1.847ns (routing 0.527ns, distribution 1.320ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.358     0.358 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.082     0.440                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.755 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.775     2.530                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/data_out_reg
    SLICE_X96Y160        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X96Y160        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.114     2.644 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/Q
                         net (fo=6, routed)           0.677     3.321                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/AS[0]
    SLICE_X98Y160        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_2 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.847     5.376                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/CLK
    SLICE_X98Y160        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]/C
                         clock pessimism              0.000     5.376                           
                         clock uncertainty           -0.035     5.341                           
    SLICE_X98Y160        FDPE (Recov_AFF2_SLICEL_C_PRE)
                                                     -0.082     5.259    AG_niop                niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]
  -------------------------------------------------------------------
                         required time                          5.259                           
                         arrival time                          -3.321                           
  -------------------------------------------------------------------
                         slack                                  1.937                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/data_out_reg/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/sync1_r_reg[0]/PRE
                            (removal check against rising-edge clock rxoutclk_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_2 rise@0.000ns - rclkp rise@0.000ns)
  Data Path Delay:        0.312ns  (logic 0.049ns (15.705%)  route 0.263ns (84.295%))
  Logic Levels:           0  
  Clock Path Skew:        0.252ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.289ns
    Source Clock Delay      (SCD):    1.037ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.758ns (routing 0.252ns, distribution 0.506ns)
  Clock Net Delay (Destination): 1.124ns (routing 0.346ns, distribution 0.778ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.161     0.161 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.018     0.179                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.279 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.758     1.037                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/data_out_reg_0
    SLICE_X95Y159        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/data_out_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X95Y159        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.049     1.086 f  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/coreclk_reset_rx_sync_i/data_out_reg/Q
                         net (fo=5, routed)           0.263     1.349                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/AS[0]
    SLICE_X95Y161        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/sync1_r_reg[0]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y10  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.124     1.289                         niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/CLK
    SLICE_X95Y161        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     1.289                           
    SLICE_X95Y161        FDPE (Remov_HFF2_SLICEL_C_PRE)
                                                      0.005     1.294    AG_niop                niop/bnk/genblk2[0].genblk1[2].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxreset_rxusrclk2_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.294                           
                         arrival time                           1.349                           
  -------------------------------------------------------------------
                         slack                                  0.055                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2
  To Clock:  rxoutclk_3

Setup :            0  Failing Endpoints,  Worst Slack        0.657ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.753ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.657ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].p2d/xrst_reg/C
                            (rising edge-triggered cell FDSE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[6]/CLR
                            (recovery check against rising-edge clock rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_3 rise@3.200ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        1.832ns  (logic 0.233ns (12.718%)  route 1.599ns (87.282%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.594ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.113ns = ( 5.313 - 3.200 ) 
    Source Clock Delay      (SCD):    2.707ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.310ns (routing 0.623ns, distribution 1.687ns)
  Clock Net Delay (Destination): 1.784ns (routing 0.520ns, distribution 1.264ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.082     0.082                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.397 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        2.310     2.707                         niop/bnk/genblk2[0].genblk1[3].p2d/txusrclk2
    SLICE_X94Y265        FDSE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/xrst_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X94Y265        FDSE (Prop_HFF2_SLICEM_C_Q)
                                                      0.117     2.824 f  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/xrst_reg/Q
                         net (fo=3, routed)           0.318     3.142                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/xrst
    SLICE_X91Y262        LUT2 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.116     3.258 f  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vordx_i_2__2/O
                         net (fo=66, routed)          1.281     4.539                         niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[0]_0
    SLICE_X91Y279        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[6]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_3 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.784     5.313                         niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/clk
    SLICE_X91Y279        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[6]/C
                         clock pessimism              0.000     5.313                           
                         clock uncertainty           -0.035     5.278                           
    SLICE_X91Y279        FDCE (Recov_CFF2_SLICEL_C_CLR)
                                                     -0.082     5.196    AG_niop                niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[6]
  -------------------------------------------------------------------
                         required time                          5.196                           
                         arrival time                          -4.539                           
  -------------------------------------------------------------------
                         slack                                  0.657                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.753ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].p2d/s_ena_reg/C
                            (rising edge-triggered cell FDRE clocked by gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2  {rise@0.000ns fall@1.600ns period=3.200ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[0]/CLR
                            (removal check against rising-edge clock rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_3 rise@0.000ns - gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise@0.000ns)
  Data Path Delay:        0.772ns  (logic 0.101ns (13.083%)  route 0.671ns (86.917%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.224ns
    Source Clock Delay      (SCD):    1.210ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      1.092ns (routing 0.339ns, distribution 0.753ns)
  Clock Net Delay (Destination): 1.059ns (routing 0.345ns, distribution 0.714ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_2 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y8   GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[0].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK
                         net (fo=2, routed)           0.018     0.018                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i_0
    BUFG_GT_X0Y48        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.118 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_gt_i/O
    X2Y2 (CLOCK_ROOT)    net (fo=9735, routed)        1.092     1.210                         niop/bnk/genblk2[0].genblk1[3].p2d/txusrclk2
    SLICE_X91Y263        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/s_ena_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X91Y263        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.048     1.258 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/s_ena_reg/Q
                         net (fo=4, routed)           0.078     1.336                         niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/s_ena
    SLICE_X91Y262        LUT2 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.053     1.389 f  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/f_i/bif/vordx_i_2__2/O
                         net (fo=66, routed)          0.593     1.982                         niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[0]_0
    SLICE_X91Y278        FDCE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[0]/CLR
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_3 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.059     1.224                         niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/clk
    SLICE_X91Y278        FDCE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[0]/C
                         clock pessimism              0.000     1.224                           
    SLICE_X91Y278        FDCE (Remov_BFF2_SLICEL_C_CLR)
                                                      0.005     1.229    AG_niop                niop/bnk/genblk2[0].genblk1[3].p2d/p_i/vfa/vcnt_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.229                           
                         arrival time                           1.982                           
  -------------------------------------------------------------------
                         slack                                  0.753                           





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  rclkp
  To Clock:  rxoutclk_3

Setup :            0  Failing Endpoints,  Worst Slack        1.973ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.047ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.973ns  (required time - arrival time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]/PRE
                            (recovery check against rising-edge clock rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.200ns  (rxoutclk_3 rise@3.200ns - rclkp rise@0.000ns)
  Data Path Delay:        0.697ns  (logic 0.114ns (16.356%)  route 0.583ns (83.644%))
  Logic Levels:           0  
  Clock Path Skew:        -0.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.100ns = ( 5.300 - 3.200 ) 
    Source Clock Delay      (SCD):    2.512ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.489ns, distribution 1.268ns)
  Clock Net Delay (Destination): 1.771ns (routing 0.520ns, distribution 1.251ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.358     0.358 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.082     0.440                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.315     0.755 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         1.757     2.512                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/data_out_reg
    SLICE_X98Y177        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X98Y177        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.114     2.626 f  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_reg__0/Q
                         net (fo=6, routed)           0.583     3.209                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/AS[0]
    SLICE_X98Y178        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_3 rise edge)
                                                      3.200     3.200 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     3.200 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.046     3.246                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.283     3.529 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.771     5.300                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/CLK
    SLICE_X98Y178        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]/C
                         clock pessimism              0.000     5.300                           
                         clock uncertainty           -0.035     5.265                           
    SLICE_X98Y178        FDPE (Recov_AFF2_SLICEL_C_PRE)
                                                     -0.082     5.183    AG_niop                niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/cable_pull_logic_i/cable_pull_reset_rising_rxusrclk2_sync_i/sync1_r_reg[1]
  -------------------------------------------------------------------
                         required time                          5.183                           
                         arrival time                          -3.209                           
  -------------------------------------------------------------------
                         slack                                  1.973                           





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.047ns  (arrival time - required time)
  Source:                 niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/pma_resetout_rising_reg/C
                            (rising edge-triggered cell FDRE clocked by rclkp  {rise@0.000ns fall@3.200ns period=6.400ns})
  Destination:            niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/pma_resetout_rising_rxusrclk2_sync_i/sync1_r_reg[0]/PRE
                            (removal check against rising-edge clock rxoutclk_3  {rise@0.000ns fall@1.600ns period=3.200ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (rxoutclk_3 rise@0.000ns - rclkp rise@0.000ns)
  Data Path Delay:        0.224ns  (logic 0.049ns (21.875%)  route 0.175ns (78.125%))
  Logic Levels:           0  
  Clock Path Skew:        0.172ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.222ns
    Source Clock Delay      (SCD):    1.050ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.771ns (routing 0.252ns, distribution 0.519ns)
  Clock Net Delay (Destination): 1.057ns (routing 0.345ns, distribution 0.712ns)

    Location             Delay type                Incr(ns)  Path(ns)    PBlock               Netlist Resource(s)
  -------------------------------------------------------------------    ----------------------------------------
                         (clock rclkp rise edge)      0.000     0.000 r                       
    GTHE3_COMMON_X0Y1                                 0.000     0.000 r                       rclkp (IN)
                         net (fo=0)                   0.000     0.000                         sc/rclkp
    GTHE3_COMMON_X0Y1    IBUFDS_GTE3 (Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2)
                                                      0.161     0.161 r                       sc/mgtr/ODIV2
                         net (fo=2, routed)           0.018     0.179                         niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i_0
    BUFG_GT_X0Y38        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.100     0.279 r  AG_niop              niop/bnk/ten_gig_eth_pcs_pma_shared_clock_reset_block/refclk_bufg_gt_i/O
    X3Y2 (CLOCK_ROOT)    net (fo=583, routed)         0.771     1.050                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/CLK
    SLICE_X95Y171        FDRE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/pma_resetout_rising_reg/C
  -------------------------------------------------------------------    ----------------------------------------
    SLICE_X95Y171        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.049     1.099 f  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/pma_resetout_rising_reg/Q
                         net (fo=7, routed)           0.175     1.274                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/pma_resetout_rising_rxusrclk2_sync_i/sync1_r_reg[0]_0[0]
    SLICE_X96Y172        FDPE                                         f  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/pma_resetout_rising_rxusrclk2_sync_i/sync1_r_reg[0]/PRE
  -------------------------------------------------------------------    ----------------------------------------

                         (clock rxoutclk_3 rise edge)
                                                      0.000     0.000 r                       
    GTHE3_CHANNEL_X0Y11  GTHE3_CHANNEL                0.000     0.000 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_gt_i/inst/gen_gtwizard_gthe3_top.tge_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK
                         net (fo=2, routed)           0.035     0.035                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk
    BUFG_GT_X0Y64        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.165 r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/rxoutclk_bufg_gt_i/O
    X3Y3 (CLOCK_ROOT)    net (fo=1051, routed)        1.057     1.222                         niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/pma_resetout_rising_rxusrclk2_sync_i/sync1_r_reg[4]_0
    SLICE_X96Y172        FDPE                                         r  AG_niop              niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/pma_resetout_rising_rxusrclk2_sync_i/sync1_r_reg[0]/C
                         clock pessimism              0.000     1.222                           
    SLICE_X96Y172        FDPE (Remov_HFF2_SLICEL_C_PRE)
                                                      0.005     1.227    AG_niop                niop/bnk/genblk2[0].genblk1[3].ten_gig_eth_pcs_pma_block_i/tge_0_local_clock_reset_block/pma_resetout_rising_rxusrclk2_sync_i/sync1_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.227                           
                         arrival time                           1.274                           
  -------------------------------------------------------------------
                         slack                                  0.047                           





