Help: ICE_GENERAL_SHARCMEM
SHARC/PPC Memory Allocation
The controller chip on series 2 and 3 cards, has two 128kBy blocks of
internal memory. The lower half is used for the sequencer logic and user programs.
The upper block contains the circular buffers for DMA channels.
The DMA block is divided as follows:
word addr range usage
0x28000-29FFF Module-1
0x2A000-2BFFF Module-2
0x28000-2BFFF Module-1 VHS
0x2C000-2FFFF Module-2 VHS
0x2C000-2CFFF Tuner-A (MBT2/MBT3)
0x2D000-2DFFF Tuner-B (MBT2/MBT3)
0x2E000-2EFFF Tuner-C (MBT2/MBT3)
0x2F000-2FFFF Tuner-D (MBT2/MBT3)
0x28000-28FFF Tuner-E (MBT2/MBT3)
0x2A000-2AFFF Tuner-F (MBT2/MBT3)
0x2E000-2EFFF Tuner-1 (PIC2/PIC3)
0x2F000-2FFFF Tuner-2 (PIC2/PIC3)
0x28000-28FFF Internal-1
0x29000-29FFF Internal-2
0x2A000-2AFFF Internal-3
0x2B000-2BFFF Internal-4
0x2C000-2CFFF Internal-5
0x2D000-2DFFF Internal-6
0x2E000-2EFFF Internal-7
0x2F000-2FFFF Internal-8
The SHARC controller chip on series 4 cards, has two 256kBy blocks of internal
memory. The lower half is used for the sequencer logic and user programs.
The upper block contains the circular buffers for DMA channels.
The DMA block is divided as follows:
word addr range usage
0x48000-49FFF Module-1
0x4A000-4BFFF Module-2
0x48000-4BFFF Module-1 VHS
0x4C000-4FFFF Module-2 VHS
0x4C000-4DFFF Tuner-A (PIC4/MBT4)
0x4E000-4FFFF Tuner-B (PIC4/MBT4)
0x48000-48FFF Internal-1
0x49000-49FFF Internal-2
0x4A000-4AFFF Internal-3
0x4B000-4BFFF Internal-4
0x4C000-4CFFF Internal-5
0x4D000-4DFFF Internal-6
0x4E000-4EFFF Internal-7
0x4F000-4FFFF Internal-8
0x50000-51FFF External-1 or ITDEC Channel-1
0x52000-53FFF External-2 or ITDEC Channel-2
0x54000-55FFF External-3 ...
0x56000-57FFF External-4
0x58000-59FFF External-5
0x5A000-5BFFF External-6
0x5C000-5DFFF External-7
0x5E000-5FFFF External-8
Note that some of the memory buffers overlap and cannot be used simultaneously.
Currently no internal checks are made to notify users of overlap.