Help: ICE_FLAGS_PORT=PORT
This specifies the default port type and index for the pic_ioport() library.
This specifies the default port type and index for the pic_ioport() library.
The syntax may also include the processor module index. For example:
PORT=CORE2 - the 2nd FPGA core on the default processor module (generic)
PORT=PM2CORE1 - the 1st FPGA core on processor module 2 (specific)
PORT=PM0TUNER2 - the 2nd tuner on the main board (specific)
PORT=TUNER33 - the 1st tuner on processor module 2 (generic)
The generic port indexing syntax will automatically place the port resource on
the preferred module. For instance, if there are two processor modules of the
same type defined, the TUNER ports will be spread across them. However, the
tuners on the main board (PM0) will not be used. This method properly addresses
most use cases.
The specific port indexing syntax allows the user to specify the processor module
and the index of the port resource on that module. This is the only way to also
use the main board TUNER and CORE resources when a processor module is defined.
See help on PIC_IOPORT for more details.
See help on PMI=n .
Port resources that are not IO ports, like TUNERs and COREs, are fed by the
MODULE on the same side of the card unless the INP or IPORT flags are used.