Help: ICE_IOC_8E1
Dual asynchronous 8 clock/data pairs
In 8E1/E1MUX mode, the IOC expects 8 E1 clock and data lines. The 8 serial
streams are optionally processed for sync and output on frame boundaries.
Data is copied to the host buffer in pairs of 32 bit packed words, oriented
as 32b channel number followed by 32b data word. The host then demultiplexes
the 32 bit data words to multiple continuous output streams.
To run 8E1 the IOC must be loaded with:
pic reset <card alias> "8e1" from Midas
pic_loadfile (p, "*_8e1", FLG_IOC); from C
The IOPORT call must include the flag FLG_DUAL.
The connector from LSB to MSB in 8E1 mode is defined as:
dat0,clk0,dat1,clk1, ... dat7,clk7 with BIT=0 flag (default)
clk0,dat0,clk1,dat1, ... clk7,dat7 with BIT=1 flag
The KEY_IOCALG byte registers are as follows:
KEY_IOCALG+0 datinv[7..0] inverts the input data if channel bit is set
KEY_IOCALG+1 clkinv[7..0] inverts the input clock if channel bit is set
KEY_IOCALG+2 usesync[7..0] only output on frame boundaries where E1 sync found
KEY_IOCALG+3 disable[7..0] disables input if channel bit is set
Use
pic_setkey(p,dmac,KEY_IOCALG+0,datinv,1);
pic_setkey(p,dmac,KEY_IOCALG+1,clkinv,1);
pic_setkey(p,dmac,KEY_IOCALG+2,usesync,1);
pic_setkey(p,dmac,KEY_IOCALG+3,disable,1);
or if these four bytes are packed into 1 int_4 register,
pic_setkey(p,dmac,KEY_IOCALG,®ister,4);
or
pic_setkeyl(p,dmac,KEY_IOCALG,register);