Help: ICE_FLAGS_CLKI

Invert input clock


Input data cycles are defined by the rising edge of the input clock.  
Data is assumed to be stable in the middle of the cycle.
Therefore, data is clocked in on the falling edge of the clock.  

This flag may be used to invert the input clock when the data source
uses the opposite convention.

Output data cycles are defined by the rising edge of the output clock.
Data will change on the rising edge of the clock, and will be stable at
the falling edge of this clock.  When stopped and during configuration, 
the clock is high.  When enabled, clock goes low.  The clock will then 
go high and low for each valid sample.  When disabled, clock will return 
high.

This flag may be used to invert this clock output convention.
Data will change on the falling edge of the clock, and will be stable at
the rising edge of the clock.  When stopped and during configuration, 
the clock is high.  The clock will then go low and high for each valid sample.  
When disabled, clock will stay high.