Help: ICE_CARDS_A2D
Analog to Digital Converter Module
This module converts analog signal voltages to 12-bit TTL at up to 65MHz.
Signal lines are attached to the module by two coaxial cables, clock and data.
NOTE: The AD6620 has a minimum clock rate of 5MHz.
SERIES 2 CARDS:
The data is 1Vpp into 50 Ohms through a 1:4 RF transformer.
The clock is jumpered to be DC coupled TTL levels, an AC coupled 1Vpp sine wave,
or a crystal installed on the module (optional).
The clock also has a jumper that applies a 50 ohm termination to ground.
An internal clock from the mother board is also available via software control.
It is the on-board crystal 40MHz divided by an integer from 1 to 65535.
Jumper Settings:
H3 - Closed for 50 ohm termination
H4 - Closed for DC coupled clock input (0-5V)
H5 - Closed for AC coupled clock input (1Vpp)
H6 - Closed for on-board oscillator clock input
The clock and data are brought out to the edge connector as follows:
Upper - A side data
UMid - A side clock
LMid - B side clock
Lower - B side data
SERIES 3 CARDS:
The data is 1Vpp into 50 Ohms through a 1:4 RF transformer.
The clock is an AC coupled 1Vpp sine wave with 50ohm termination jumper.
Two clocks from the mother board are also available via software control.
The internal clock (MUXCLK=I) is the on-board 40MHz crystal divided by an
integer from 1 to 65535. A second socketed crystal (default=65MHz) is
available as (MUXCLK=C).
Jumper Settings:
J1 - Closed to ground data connector sleeve
J2 - Closed to ground clock connector sleeve
J3 - Closed for 50 ohm termination of clock
The clock is the upper SMB and the data is the lower SMB per module.
Note that the series 3 edge connector has its own SMB for the eXternal
clock/sync signal. To use this clock apply the MUXCLK=X flag.
If both modules are A2Ds the SMBs will be ordered as:
Upper - A side data
UMid - A side clock
Middle- External clock/sync
LMid - B side data
Lower - B side clock