Help: ICE_GENERAL_TIMECODE

Handling Embedded TimeCode


Digital time code embedded in the input stream is processed by library routines 
that run on the host computer.  Double clutch timecode is handled automatically.

When acquiring data, the timecode bit from the raw input is processed in the 
FPGA with a defined Barker code. The timecode is tagged with the 
sample number and the last two stored in the FPGA's memory.  Host code queries 
the FPGA for this information and maps the timecode to a specified index in the 
host acquisition buffer.  This allows time tagging 8 or 16 bit packed data, 
as well as the on-board tuner output.  The delay through the tuner chips is
is compensated for in the host software. See HELP PIC_TC.

Digital IRIG-B input to the external trigger port is processed by the IOC FPGA
into a barker code and 32 bits of data much like the other digital time code 
standards.  The accuracy is about 100uS on most GPS receivers.  The A2Dr7
modules have an optional 1PPS port that can be used to refine the measurement
to the accuracy of the 1PPS +- 10nS.

If a computer has NTP enabled (Network Time Protocol), only the 1PPS is needed
to provide and accurate time stamp.

SDDS embeds the timecode in a packet header.  This is read by the IOC and 
handled downstream in the same way embedded serialized timecode is handled.

The PIC5 series can also process serialized SDN timecode embedded in the SDDS
payload section.  To enable this, simply specify TC=SDN0 (or TC=SDN3 for some
tape playback scenarios).

The PIC4 series handles this case with special setup steps.  The I/O Module
must use the RXSDDSDATA flag to to eat the SDDS packet headers and present the
PIC4 with normal 16 bit data.  This is then processed by the normal IOC=II or 
IOC=IO FPGA load which handles the SDN timecode.  Since the default download 
for an SDDS module is IIS or IOS, the IOC code must be specified in the card reset.