Help: ICE_FLAGS_FIRONLY

Bypasses the front end of the FPGA based tuners (PIC5+)


Bypasses the front end of the FPGA based tuners (PIC5+).  The back end PFIR 
filter elements are used to implement a full rate 63|127 tap filter at 64|32MHz.  

If the special Filter Only core is loaded (SoC signature SSF or HHF) this flag
will allow the KEY_GAIN settings in sourcepic to compensate for attenuation in
the filter taps.  If the filter is loaded with the FFIR=name flag, compensation
for the known filter attenuation/gain is added to this value.  If the filter is
loaded through a separate LOADFC command, the gain setting must include the 
compensation for the filter attenuation/gain.