Help: ICE_GENERAL_DMA

DMA Concepts and Channel Allocation


High speed data transfer is via the PCI controller's DMA engine which is given
maximum hardware-level priority since the card has minimal buffer memory.  The
host computer typically allocates a circular buffer in memory to hold 1-2
seconds of data (to cover host application software latencies).  The SHARC/PPC
then processes DMA requests from 1 to 80 of it's input/output ports.
All 80 DMA channels can be owned/controlled by different processes.

Acquisition/Playback can occur through the following device ports:

  SERIAL1-2   : serial ports (PIC2 only)
  LINK1-6     : link ports (PIC2 only)
  TUNER1-32   : tuner channels
  MODULE1-2   : I/O Modules
  INTERNAL1-8 : internal algorithms
  EXTERNAL1-8 : internal algorithms (extended memory on PIC4/MBT4)

The port is usually specified in the hardware configured device alias. 
See HELP PIC_OPEN for details, HWCONFIG.KEY in the DAT area for examples.

There are 8 hardware DMA channels on the SHARC that are shared between the 
ports.  This means that up to 8 hardware acquisitions/playbacks can be 
occurring simultaneously on a single ICE card.  There are also internal
algorithms executing on the SHARC that may also produce or consume DMA
data buffers.

The FPGA on the 5 series cards allow each DMA channel to have its own port 
so there are no resource conflicts.  The PPC is a controller only.  Its DMA
resources are not used to handle data.

A serial port is tied to its DMA channel.  A link port can be associated with
any DMA channel supporting a link buffer.  The DMA channel will be determined 
automatically from the port name.  

The user is responsible for managing any sharing of the serial port, 
tuner/serial port, link port, and module/link port DMA resources.  

The DMA Channel mappings for ICE-PIC2 are:
  Chan 1	Serial Port 1 Receive			SERIAL1/TUNER1
  Chan 2	Serial Port 2 Receive  or Link Buf 1	SERIAL2/TUNER2/LINK1
  Chan 3	Serial Port 1 Transmit			SERIAL1
  Chan 4	Serial Port 2 Transmit or Link Buf 2	SERIAL2/LINK2
  Chan 5	Link Buffer 3 				LINK3/MODULE1
  Chan 6	Link Buffer 4 				LINK4/MODULE2
  Chan 7	Link Buffer 5           		LINK5/MODULE1HS
  Chan 8	Link Buffer 6            		LINK6/MODULE2HS

The DMA Channel mappings for ICE-PIC3 are:
  Chan 2	Link Buffer 1				TUNER-A
  Chan 4	Link Buffer 2				TUNER-B
  Chan 5	Link Buffer 3 				MODULE1HS
  Chan 6	Link Buffer 4 				MODULE2HS
  Chan 7	Link Buffer 5 				MODULE1
  Chan 8	Link Buffer 6 				MODULE2

The DMA Channel mappings for ICE-MBT2 and ICE-MBT3 are:
  Chan 2	Link Buffer 1				TUNER-A
  Chan 4	Link Buffer 2				TUNER-B
  Chan 5	Link Buffer 3 				TUNER-C/MODULE1HS
  Chan 6	Link Buffer 4 				TUNER-D/MODULE2HS
  Chan 7	Link Buffer 5 				TUNER-E/MODULE1
  Chan 8	Link Buffer 6 				TUNER-F/MODULE2

Each tuner chip uses one of the sharc link ports for acquiring the tuner 
outputs.  The four channels in each tuner chip must have the same decimation. 
Tuner channels are allocated such that odd and even channel numbers are fed 
by modules 1 and 2 respectively.  See the allocation chart below:

  TUNER-A	Channels 1,3,5,7	Link Port 1 
  TUNER-B	Channels 2,4,6,8	Link Port 2 
  TUNER-C	Channels 9,11,13,15	Link Port 3 
  TUNER-D	Channels 10,12,14,16	Link Port 4 
  TUNER-E	Channels 17,19,21,23	Link Port 5 
  TUNER-F	Channels 18,20,22,24	Link Port 6 

The ICE-MBT3 can also collect wide-signals bypassing the tuner chips.  Since 
the wideband paths and the tuners share the link ports, resource contention 
occurs.  If the wideband transfer is < 38Mby/sec, only link ports 5 or 6 are 
used.  If the wideband transfer is >= 38 Mby/sec, Module 1 will take link 
ports 5 and 3, and Module 2 will take link ports 6 and 4.  This means that 
tuners C through F may be unusable while processing wideband simultaneously.  

The DMA Channel mappings for ICE-PIC4T and ICE-MBT4 are:
  Chan 5	Link Buffer 1 				MODULE1
  Chan 6	Link Buffer 2 				MODULE2
  Chan 7	Link Buffer 3 				MODULE1HS
  Chan 8	Link Buffer 4 				MODULE2HS
  Chan 9	Link Buffer 5				TUNER-N odd
  Chan 10	Link Buffer 6				TUNER-N even

There is no link port sharing between tuners and modules on the series 4 cards.
All odd tuners are multiplexed through DMA channel 9 and all even channels through 
DMA channel 10.  The data is demultiplexed by the SHARC into separate host buffers.

The DMA Channel mappings for ICE-PIC5+ Input/Output are:
  Chan 1        MODULE1
  Chan 2        MODULE2
  Chan 3        CORE1 / TUNER1
  Chan 4        CORE2 / TUNER2
  Chan 5        CORE11
  Chan 6        CORE12
  Chan 7        CORE21
  Chan 8        CORE22
  Chan 9        MCORE11 / TBANK11 / TUNER1-31
  Chan 10       MCORE12 / TBANK12 / TUNER2-32
  Chan 11       MCORE21 / TBANK21 / TUNER33-63
  Chan 12       MCORE22 / TBANK22 / TUNER34-64

Access to the ICEMBT ports is made transparent via software such that the 
PICDRIVER and SOURCEPIC primitives may access a port on an ICE-MBT just as 
they would a port on an ICE-PIC.