Help: ICE_IOC



This file contains a brief text description of the currently available code
downloads for the Altera IOC (I/O Controller) Chip.  Standard Input/Output
configurations handle packing/unpacking of 1|4|8|16 bit data words, gating,
triggering, embedded timecode, and module programming.

The mux clock options are controlled by the MUXCLK=s flag. See Help on MUXCLK flag.

  II - Mod1=StdInput Mod2=StdInput
  IIX - Mod1=StdInput Mod2=StdInput with mux clock
  IIR - Mod1=StdInput Mod2=StdInput with internally generated ramp
  IIS - Mod1=SDDSInput Mod2=SDDSInput with packet handlers
  IO - Mod1=StdInput Mod2=StdOutput
  IOX - Mod1=StdInput Mod2=StdOutput with mux clock
  OO - Mod1=StdOutput Mod2=StdOutput
  OOY - Mod1=StdOutput Mod2=StdOutput with independent clocks

  OOW - Mod1&2 internally generated white noise with timecode
  T1 - Test internal loopback module 2 out to module 1 in
  T2 - Test internal loopback module 1 out to module 2 in


  E321 - Dual E3 to 16xE1 Demux w/ optional sync
  8E1 - Dual asynchronous 8 clock/data pairs
  GSM - Dual E1 channelizer/unpacker
  FMDE - Handles framing of FMDE signals
  BP - Handles bit packing of 1,2,3,4,5,6,7 or 8 bit data

The Standard Input/Output configurations are loaded automatically during a
pic_reset according to the specified module configuration.  The non-standard
IOC downloads can be performed during a reset using the IOC=xxxx flag, or 
after a reset by calling pic_loadfile.  From Midas, this is an optional 
parameter on PICDRIVER, ie: PICD RESET PIC1 8E1

For PIC5 and later cards, the IOC= setting is not actually a FPGA download file,
but a register setting in the SoC download to implement that function.
The specific algorithms E321 ... BP would be handled in FPGA cores loaded onto
processor modules or the main board in some cases.