Help: ICE_FLAGS_OPPSOFFSET=N
Number of clock cycles offset between the 1PPS signal capture and the data capture.
Number of clock cycles offset between the 1PPS signal capture and the data capture.
A positive value means the 1PPS precedes the actual data it corresponds to by N samples.
An A2D, for instance, often has 4 data pipeline stages between its input and output,
but typically the 1PPS signal is captured coincident with the A2Ds output register.
The 1PPS, if captured with the LSBX flag, will show up in the data stream 4 samples
earlier than the data it corresponds to.
This defaults to the value +4 for A2D modules, and 0 for all others. Some modules,
like the FCXD or LVDS will need to set this when being driven by an A2D or some
other source with pipeline delays relative to the 1PPS.