Help: ICE_ICELIB_PIC_TUNER_DEC
Returns the nearest supported decimation
Function PIC_TUNER_DEC - Returns the nearest supported decimation
PIC p Handle to Device
int dec Tuner decimation desired
int port Index of port to use
int flags Run-time modifiers
Returns:
int PIC_TUNER_DEC Actual supported decimation
This routine returns the nearest possible decimation supported by the
specified device. Each chip has different limitations.
HSP50016 ICEPIC2
AD6620 ICEPIC3
GC4014 ICEMBT2/ICEMBT3/ICESLIC3
GC4016 ICEPIC4/ICEMBT4/ICEMBT5
FPGA ICEPIC5
The Harris HSP50016 DDC decimation is 36 to 32768 in steps of 2.
The Graychip GC4014 in CPC=4 mode is 32 to 32768 in steps of 2.
The Graychip GC4014 in CPC<4 mode is 16 to 32768 in steps of 2.
These limitations are from using the GC's link port output mode.
The Graychip GC4016 in CPC=4 mode is 16 to 4096 in steps of 2.
The Graychip GC4016 in CPC=2 mode is 8 to 2048 in steps of 2.
The Graychip GC4016 in CPC=1 mode is 4 to 2048 in steps of 2.
The FPGA Core is 2 to 4096 in steps of 2.
On main board, the FPGA core also supports decimate by 1.
On processor module, the FPGA core minimum decimation is 4.
The Analog Devices AD6620 decimation is 1 to 16384 in steps supported
by the cascaded filters described below.
The Analog Devices AD6620 has a 2 stage decimator where the 1st stage can
decimate from 1 to 16 and the second from 1 to 32. The final FIR filter
stage can also decimate by 1,2,4,8 or 16 to support the higher decimations.
Default filters for each FIR decimation are supplied. This routine implements
the algorithm to find the nearest possible decimation resulting from the
cascaded filter stages.
The AD6620 FIR filter can only process one complex output tap per system clock.
At input sample rates < 16MHz, oversampling will be set to OVSR=1, switching
the system clock to the 65MHz on-board crystal oscillator.