Help: ICE_SOC



This file contains a brief text description of the currently available code
downloads for the Xilinx System On a Chip FPGAs. 

Processor Modules implement the module control/data interface, memory controller,
specialty chip (tuner) interfaces, and processor cores in a single Virtex chip.

The 5+ series cards implement the PCI interface, module control/data interfaces, 
memory controller, processor cores, and IO controller in a single Virtex chip.

The SOC's IO controller implements all of the IOC modes in the default load.
The IOC=s settings that are downloads on pre series 5 cards are operational 
register sets on series 5+ cards.

All SoC downloads contain a 4-character configuration signature.
The first two characters describe the I/O or processor module interface types. 
The third and fourth characters specify the internal functional cores 1 & 2.
If the fourth character is blank, it is the same as core 1.

The supported I/O module interface configurations are
  S: SingleEnded used for E2D,D2E, T2D,D2T, LV2D,D2LV, A2DR8,D2AR8 modules.
  D: Differential used for DR2D, RFXD, A2DR14
  H: HyperTransport used for SNTR5XD, SDDSXD,TGSDDSXD, A2DR9,D2AR9, A2DR10,A2DR11,A2DR13, LB2D modules.
  R: RocketIO used for MSASXD, DSFPXD

The processor module data interface configurations are
  S: SingleEnded used for modules on PIC4X 
  H: HyperTransport used for modules on PIC5 and later

The supported Core configurations are
  N: Noop Engine 
  F: Filter Engine 
  D: Demod (2-D LUT) Engine (default on DTDMs)
  T: Tune/Filter/Decimate/Resample/Demod Engine (default on PICs)
  U: User Engine (Customer specific Upsampler in current release)
  V: Vita-49 Radio Transport
  G: GSM Engine

The currently supported combinations of I/O and Core configurations are 

  SS - Mod1=SingleEnded Mod2=SingleEnded
  HH - Mod1=HyperTransport Mod2=HyperTransport
  SH - Mod1=SingleEnded Mod2=HyperTransport
  SSN - Mod1=SingleEnded Mod2=SingleEnded Core=Noop
  HHN - Mod1=HyperTransport Mod2=HyperTransport Core=Noop
  HHF - Mod1=HyperTransport Mod2=HyperTransport Core=Filter
  HHTF - Mod1=HyperTransport Mod2=HyperTransport Core1=Tuner Core2=Filter
  HHTQ - Mod1=HyperTransport Mod2=HyperTransport Core1=Tuner Core2=QuickTuner

The SoC code is programmed into the FPGA's boot EPROM with the flash utility.  

For example,        PICDRIVER LOADFLASH PIC1 ICEPIC5_SSN

This takes roughly three minutes.  Take note of the verification info.
If this reads back with zero errors, you are ready to reboot the card.

If there are errors, do NOT power off or reboot.  Repeat the loadflash
until it returns with zero errors. If the card is rebooted with a bad
flash, please call the factory.  You will have to return it or use a 
2nd PIC5+ card to reload the dead card's flash.  This involves a standard 
14 pin JTAG cable with special jumper settings.

Linux systems can use a live reboot feature to reload the SOC.

For example,        PICDRIVER SET PIC1 FLASH 999 

All other systems will need to power down the machine, and reboot.
To verify the reboot use PICDRIVER DETECT.  
The output will look something like

  nM> pic detect
  CARD #0 Type=PIC4  (Up/Idle)
    Interface  Type=PCI ChipRev=9 Bus=32b Clk=33MHz  Endian=0 Driver=317
    Modules    Iom1=UNKNOWN Iom2=UNKNOWN
    FirmWare   Proc=318 Ioc=OOW
  CARD #1 Type=PIC5  (Up/Idle)
    Interface  Type=PCI ChipRev=3 Bus=64b Clk=66MHz+ Endian=0 Driver=317
    Modules    Iom1=NONE Iom2=NONE Pm1=DTDMX:DEF  Pm2=DTDM:DEF
    FirmWare   Proc=318 Ioc=II   SoC Ver=318 Sig=HH

The Soc version and signature line should show the new load.

Each SoC flash for an ICE release has an associated CRC value. 
See the release notes section on NON-VOLATILE for the procedure to
validate the currently loaded flash CRC.